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SPC560B50L5 Schematic ( PDF Datasheet ) - ST Microelectronics

Teilenummer SPC560B50L5
Beschreibung 32-bit MCU family built on the Power Architecture embedded category
Hersteller ST Microelectronics
Logo ST Microelectronics Logo 




Gesamt 30 Seiten
SPC560B50L5 Datasheet, Funktion
www.DataSheet4U.com
SPC560B40x, SPC560B44x, SPC560B50x
SPC560C40x, SPC560C44x, SPC560C50x
32-bit MCU family built on the Power Architecture® embedded
category for automotive body electronics applications
Features
High-performance 64 MHz e200z0h CPU
– 32-bit Power Architecture® technology
– Up to 60 DMIPs operation
– Variable length encoding (VLE)
Memory
– Up to 512 Kbytes Code Flash, with ECC
– 64 Kbytes Data Flash, with ECC
– Up to 48 Kbytes SRAM, with ECC
– 8-entry memory protection unit (MPU)
Interrupts
– 16 priority levels
– Non-maskable interrupt (NMI)
– Up to 34 ext. int. including 18 wakeup lines
GPIO: QFP64/45, QFP100/75, QFP144/123
Timer units
– 6-channel 32-bit periodic interrupt timers
– 4-channel 32-bit system timer module
– System watchdog timer
– Real-time clock timer
16-bit counter time-triggered I/Os
– Up to 56 channels with PWM/MC/IC/OC
– ADC diagnostic via CTU
Communications interface
– Up to 6 FlexCAN interfaces (2.0B active)
with 64-message objects each
– Up to 4 LINFlex/UART
– 3 DSPI / I2C
Table 1. Device summary
LQFP100 (14 x 14 x 1.4 mm)
LQFP144 (20 x 20 x 1.4 mm)
LQFP64 (10 x 10 x 1.4 mm)
10-bit A/D converter with up to 36 channels
– Up to 64 channels via external multiplexing
– Individual conversion registers
– Cross triggering unit
Dedicated diagnostic module for lighting
– Advanced PWM generation
– Time-triggered diagnostic
– PWM-synchronized ADC measurements
Clock generation
– 4 to 16 MHz fast external crystal oscillator
– 32 KHz slow external crystal oscillator
– 16 MHz fast internal RC oscillator
– 128 kHz slow internal RC oscillator
– Software-controlled FMPLL
– Clock monitoring unit
Exhaustive debugging capability
– Nexus1 on all devices
– Nexus2+ available on emulation package
Low power capabilities
– Ultra-low power standby with RTC, SRAM
and CAN monitoring
– Fast wakeup schemes
Operating temp. range up to -40 to 125 °C
Single 5 V or 3.3 V supply
Package
256 Kbyte code Flash
384 Kbyte code Flash
512 Kbyte code Flash
LQFP144 SPC560B40L5 — SPC560B44L5 — SPC560B50L5 —
LQFP100 SPC560B40L3 SPC560C40L3 SPC560B44L3 SPC560C44L3 SPC560B50L3 SPC560C50L3
LQFP64
SPC560B40L1 SPC560C40L1
LBGA208(1)
— SPC560B50L1 SPC560C50L1
— SPC560B50B2 —
1. LBGA208 available only as development package for Nexus2+
July 2010
Doc ID 14619 Rev 7
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www.st.com
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SPC560B50L5 Datasheet, Funktion
List of figures
List of figures
www.DataSheet4U.com
SPC560Bx, SPC560Cx
Figure 1.
Figure 2.
Figure 3.
Figure 4.
Figure 5.
Figure 6.
Figure 7.
Figure 8.
Figure 9.
Figure 10.
Figure 11.
Figure 12.
Figure 13.
Figure 14.
Figure 15.
Figure 16.
Figure 17.
Figure 18.
Figure 19.
Figure 20.
Figure 21.
Figure 22.
Figure 23.
Figure 24.
Figure 25.
Figure 26.
Figure 27.
Figure 28.
Figure 29.
Figure 30.
Figure 31.
Figure 32.
Figure 33.
Figure 34.
Figure 35.
SPC560Bx and SPC560Cx series block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
LQFP 64-pin configuration (top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
LQFP 100-pin configuration (top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
LQFP 144-pin configuration (top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
LBGA208 configuration. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
I/O input DC electrical characteristics definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
Start-up reset requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
Noise filtering on reset signal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
Voltage regulator capacitance connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
Low voltage monitor vs reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
Crystal oscillator and resonator connection scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70
Fast external crystal oscillator (4 to 16 MHz) electrical characteristics. . . . . . . . . . . . . . . . 71
Crystal oscillator and resonator connection scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
Equivalent circuit of a quartz crystal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
Slow external crystal oscillator (32 kHz) electrical characteristics . . . . . . . . . . . . . . . . . . . 74
ADC characteristic and error definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78
Input equivalent circuit (precise channels) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
Input equivalent circuit (extended channels) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80
Transient behavior during sampling phase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80
Spectral representation of input signal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82
DSPI classic SPI timing – master, CPHA = 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90
DSPI classic SPI timing – master, CPHA = 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91
DSPI classic SPI timing – slave, CPHA = 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91
DSPI classic SPI timing – slave, CPHA = 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92
DSPI modified transfer format timing – master, CPHA = 0. . . . . . . . . . . . . . . . . . . . . . . . . 92
DSPI modified transfer format timing – master, CPHA = 1. . . . . . . . . . . . . . . . . . . . . . . . . 93
DSPI modified transfer format timing – slave, CPHA = 0 . . . . . . . . . . . . . . . . . . . . . . . . . . 93
DSPI modified transfer format timing – slave, CPHA = 1 . . . . . . . . . . . . . . . . . . . . . . . . . . 94
Nexus TDI, TMS, TDO timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95
Timing diagram – JTAG boundary scan . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96
LQFP64 package mechanical drawing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97
LQFP100 package mechanical drawing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99
LQFP144 package mechanical drawing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100
LBGA208 package mechanical drawing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102
Commercial product code structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105
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Doc ID 14619 Rev 7

6 Page









SPC560B50L5 pdf, datenblatt
Block diagram
www.DataSheet4U.com
SPC560Bx, SPC560Cx
Table 3.
SPC560Bx and SPC560Cx series block summary (continued)
Block
Function
Reset generation module
(MC_RGM)
Memory protection unit (MPU)
Nexus development interface
(NDI)
Periodic interrupt timer (PIT)
Real-time counter (RTC)
System integration unit (SIU)
Static random-access memory
(SRAM)
System status configuration
module (SSCM)
System timer module (STM)
System watchdog timer (SWT)
Wakeup unit (WKPU)
Crossbar (XBAR) switch
Centralizes reset sources and manages the device reset sequence of the
device
Provides hardware access control for all memory references generated in a
device
Provides real-time development support capabilities in compliance with the
IEEE-ISTO 5001-2003 standard
Produces periodic interrupts and triggers
A free running counter used for time keeping applications, the RTC can be
configured to generate an interrupt at a predefined interval independent of the
mode of operation (run mode or low-power mode)
Provides control over all the electrical pad controls and up 32 ports with 16 bits
of bidirectional, general-purpose input and output signals and supports up to 32
external interrupts with trigger event configuration
Provides storage for program code, constants, and variables
Provides system configuration and status data (such as memory size and
status, device mode and security status), device identification data, debug
status port enable and selection, and bus and peripheral abort enable/disable
Provides a set of output compare events to support AUTOSAR and operating
system tasks
Provides protection from runaway code
The wakeup unit supports up to 18 external sources that can generate
interrupts or wakeup events, of which 1 can cause non-maskable interrupt
requests or wakeup events.
Supports simultaneous connections between two master ports and three slave
ports. The crossbar supports a 32-bit address bus width and a 64-bit data bus
width
12/113
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