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Teilenummer | HM62V256LFP-10SLT |
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Beschreibung | 32768-word x 8-bit Low Voltage Operation CMOS Static RAM | |
Hersteller | Hitachi | |
Logo | ||
Gesamt 14 Seiten HM62V256 Series
32,768-word × 8-bit Low Voltage Operation CMOS Static RAM
Features
• Low voltage operation SRAM
Operating Supply Voltage: 2.7 V to 3.6 V
• 0.8 µm Hi-CMOS process
• High speed
Access time: 70/85/100 ns (max)
• Low power
Standby: 0.15 µW (typ)
• Completely static memory
No clock or timing strobe required
• Directly LVTTL compatible: All inputs and outputs
ADE-203-136E (Z)
Rev. 5.0
Jun. 19, 1995
Ordering Information
Type No.
HM62V256LFP-10T
HM62V256LFP-7SLT
HM62V256LFP-10SLT
HM62V256LFP-8ULT
HM62V256LT-10
HM62V256LT-8SL
HM62V256LTM-10
HM62V256LTM-7SL
HM62V256LTM-10SL
HM62V256LTM-8UL
Access Time
100 ns
70 ns
100 ns
85 ns
100 ns
85 ns
100 ns
70 ns
100 ns
85 ns
Package
450 mil 280 pin plastic SOP (FP-28DA)
8 mm × 14 mm 32 pin TSOP (normal type) (TFP-32DA)
8 mm × 13.4 mm 28-pin TSOP (normal type) (TFP-28DA)
http://www.Datasheet4U.com
HM62V256 Series
DC Characteristics (Ta = 0 to +70°C, VCC = 2.7 V to 3.6V, VSS = 0 V)
Parameter
Symbol Min
Typ*1 Max Unit Test conditions
Input leakage current
Output leakage current
|ILI|
|ILO|
Operating power supply current
(DC)
ICCDC1
ICCDC2
Average
HM62V256-7
operating power
supply current
ICCAC1
HM62V256-8 ICCAC1
HM62V256-10 ICCAC1
ICCAC2
—
—
—
—
—
—
—
—
Standby power supply current
ISB
ISB1
—
—
—
—1
µA VSS ≤ Vin ≤ VCC
—1
µA CS = VIH or OE = VIH or WE = VIL,
VSS ≤ VI/O ≤ VCC
— 15 mA CS = VIL, others = VIH/VIL
II/O = 0 mA
— 10 mA CS ≤ 0.2 V, VIH ≥ VCC – 0.2 V,
VIL ≤ 0.2 V, II/O = 0 mA
— 30 mA min cycle, duty = 100 %,
II/O = 0 mA CS = VIL,
others = VIH/VIL
— 27
— 24
— 15 mA Cycle time ≥ 1 µs, duty = 100%
II/O = 0 mA, CS ≤ 0.2 V,
VIH ≥ VCC – 0.2 V, VIL ≤ 0.2 V
0.1 1
mA CS = VIH
0.05 50 µA Vin ≥ 0 V, CS ≥ VCC – 0.2 V,
0.05 10*2
— 0.05 4*3
Output low voltage
Output high voltage
VOL —
— 0.2 V
IOL = 20 µA
VOH
VCC –
—
—
V
IOH = –20 µA
0.2
Notes: 1. Typical values are at VCC = 3.0 V, Ta = +25°C and not guaranteed.
2. This characteristic is guaranteed only for L-SL version.
3. This characteristic is guaranteed only for L-UL version.
Capacitance (Ta = 25°C, f = 1.0 MHz)
Parameter
Symbol
Min Typ
Input capacitance*1
Cin — —
Input/output capacitance*1
CI/O
——
Note: 1. This parameter is sampled and not 100% tested.
Max
5
8
Unit
pF
pF
Test Conditions
Vin = 0 V
VI/O = 0 V
6
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6 Page HM62V256 Series
Low VCC Data Retention Characteristics (Ta = 0 to +70°C)
Parameter
Symbol Min Typ*1 Max Unit Test conditions*6
VCC for data retention
Data retention current
VDR
ICCDR
2.0 — 3.6 V
CS ≥ VCC – 0.2 V, Vin ≥ 0 V
— 0.05 27*2 µA VCC = 2.7 V, Vin ≥ 0 V
CS ≥ VCC – 0.2 V
— 0.05 7*3
— 0.05 2*4
Chip deselect to data retention time tCDR
0 — — ns See retention waveform
Operation recovery time
tR
t *5
RC
—
—
ns
Notes: 1. Typical values are at VCC = 2.7 V, Ta = 25°C and not guaranteed.
2. 9 µA max at Ta = 0 to 40°C.
3. This characteristics guaranteed for only L-SL version. 2.0 µA max at Ta = 0 to 40°C.
4. This characteristics guaranteed for only L-UL version. 0.4 µA max at Ta = 0 to 40°C.
5. tRC = read cycle time.
6. CS controls address buffer, WE buffer, OE buffer, and Din buffer. If CS controls data retention
mode, other input levels (address, WE, OE, I/O) can be in the high impedance state.
Low VCC Data Retention Timing Waveform
VCC
2.7 V
0.7 VCC
VDR
CS
0V
t CDR
Data retention mode
CS > VCC – 0.2 V
tR
12
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12 Page | ||
Seiten | Gesamt 14 Seiten | |
PDF Download | [ HM62V256LFP-10SLT Schematic.PDF ] |
Teilenummer | Beschreibung | Hersteller |
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