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ICE3BR0680JZ Schematic ( PDF Datasheet ) - Infineon Technologies

Teilenummer ICE3BR0680JZ
Beschreibung Off-Line SMPS Current Mode Controller
Hersteller Infineon Technologies
Logo Infineon Technologies Logo 




Gesamt 30 Seiten
ICE3BR0680JZ Datasheet, Funktion
Version 2.1a, 11 Jan 2012
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ICE3BR0680JZ Datasheet, Funktion
CoolSET®-F3R80
ICE3BR0680JZ
Pin Configuration and Functionality
1 Pin Configuration and Functionality
1.1 Pin Configuration with PG-DIP-7
1.2 Pin Functionality
Pin Symbol Function
1 BBA Brownout, extended Blanking
time & Auto-restart enable
2 FBB Feedback & Burst entry/exit con-
trol
3 CS Current Sense/
800V CoolMOS® Source
4 n.c. not connected
5 Drain 800V CoolMOS® Drain
BBA (Brownout, extended Blanking time & Auto-
restart enable)
The BBA pin combines the functions of brownout,
extendable blanking time for over load protection and
the external auto-restart enable. The brownout feature
is to stop the switching pulse when the input voltage is
dropped to a preset low level. The extendable blanking
time function is to extend the built-in 20 ms blanking
time for over load protection by adding an external
capacitor to ground. The external auto-restart enable
function is an external access to stop the gate
switching and force the IC to enter auto-restart mode.
It is triggered by pulling the pin voltage to less than
0.4V.
6 - (no pin)
7 VCC Controller Supply Voltage
8 GND Controller Ground
Package PG-DIP-7
FBB (Feedback & Burst entry control)
The FBB pin combines the feedback function and the
burst entry/exit control. The regulation information is
provided by the FBB pin to the internal Protection Unit
and the internal PWM-Comparator to control the duty
cycle. The FBB-signal is the only control signal in case
of light load at the Active Burst Mode. The burst entry/
exit control provides an access to select the entry/exit
burst mode level.
BBA
1
FBB 2
8 GND
7 VCC
CS (Current Sense)
The Current Sense pin senses the voltage developed
on the shunt resistor inserted in the source of the
integrated CoolMOS®. If CS reaches the internal
threshold of the Current Limit Comparator, the Driver
output is immediately switched off. Furthermore the
current information is provided for the PWM-
Comparator to realize the Current Mode.
CS
n.c.
Figure 1
3
4 5 Drain
Pin Configuration PG-DIP-7 (top view)
Drain (Drain of integrated CoolMOS®)
Pin Drain is the connection to the Drain of the
integrated CoolMOS®.
VCC (Power Supply)
The VCC pin is the positive supply of the IC. The
operating range is between 10.5V and 25V.
GND (Ground)
The GND pin is the ground of the controller.
Version 2.1a
6
11 Jan 2012
http://www.Datasheet4U.com

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ICE3BR0680JZ pdf, datenblatt
CoolSET®-F3R80
ICE3BR0680JZ
Functional Description
The Start-Up time tStart-Up before the converter output
voltage VOUT is settled, must be shorter than the Soft-
Start Phase tSoft-Start (Figure 13). By means of Soft-Start
there is an effective minimization of current and voltage
stresses on the integrated CoolMOS®, the clamp circuit
and the output rectifier and it helps to prevent
saturation of the transformer during Start-Up.
3.5 PWM Section
Oscillator
Duty Cycle
max
0.75
PWM Section
3.5.2
PWM-Latch FF1
The output of the oscillator block provides continuous
pulse to the PWM-Latch which turns on/off the
integrated CoolMOS®. After the PWM-Latch is set, it is
reset by the PWM comparator, the Soft Start
comparator or the Current -Limit comparator. When it is
in reset mode, the output of the driver is shut down
immediately.
3.5.3
Gate Driver
VCC
PWM-Latch
1
Clock
Frequency
Jitter
Soft Start
Block
Soft Start
Comparator
PWM
Comparator
Current
Limiting
FF1
1S
Gate Driver
G8 R Q
&
G9
CoolMOS®
Gate
Figure 14 PWM Section Block
50
Gate
CoolMOS®
Gate Driver
Figure 15 Gate Driver
The driver-stage is optimized to minimize EMI and to
provide high circuit efficiency. This is done by reducing
the switch on slope when exceeding the integrated
CoolMOS® threshold. This is achieved by a slope
control of the rising edge at the driver’s output (Figure
16) and adding a 50W gate turn on resistor (Figure 15).
Thus the leading switch on spike is minimized.
3.5.1
Oscillator
The oscillator generates a fixed frequency of 65KHz
with frequency jittering of ±4% (which is ±2.6KHz) at a
jittering period of 4ms.
A capacitor, a current source and current sink which
determine the frequency are integrated. The charging
and discharging current of the implemented oscillator
capacitor are internally trimmed in order to achieve a
very accurate switching frequency. The ratio of
controlled charge to discharge current is adjusted to
reach a maximum duty cycle limitation of Dmax=0.75.
Once the Soft Start period is over and when the IC goes
into normal operating mode, the switching frequency of
the clock is varied by the control signal from the Soft
Start block. Then the switching frequency is varied in
range of 65KHz ± 2.6KHz at period of 4ms.
(internal)
VGate
typ. t = 160ns
4.6V
t
Figure 16 Gate Rising Slope
Furthermore the driver circuit is designed to eliminate
cross conduction of the output stage.
Version 2.1a
12
11 Jan 2012
http://www.Datasheet4U.com

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