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CY2077 Schematic ( PDF Datasheet ) - Cypress Semiconductor

Teilenummer CY2077
Beschreibung High-accuracy EPROM Programmable Single-PLL Clock Generator
Hersteller Cypress Semiconductor
Logo Cypress Semiconductor Logo 




Gesamt 17 Seiten
CY2077 Datasheet, Funktion
CY2077
High-accuracy EPROM Programmable
Single-PLL Clock Generator
Features
High-accuracy PLL with 12-bit multiplier and 10-bit divider
EPROM programmability
3.3 V or 5 V operation
Operating frequency
390 kHz–133 MHz at 5 V
390 kHz–100 MHz at 3.3 V
Reference input from either a 10–30 MHz fundamental toned
crystal or a 1–75 MHz external clock
EPROM selectable TTL or CMOS duty cycle levels
Sixteen selectable post-divide options, using either PLL or
reference oscillator/external clock
Programmable PWR_DWN or OE pin, with asynchronous or
synchronous modes
Low jitter outputs typically
80 ps at 3.3 V/5 V
Controlled rise and fall times and output slew rate
Available in both commercial and industrial temperature ranges
Factory programmable device options
Logic Block Diagram
PWR_DWN
or OE
XTALOUT[1]
XTALIN
or
external clock
Q
10 bits
HIGH
ACCURACY
PLL
Charge
Pump
VCO
P
12 bits
Configuration
EPROM
MUX
/ 1, 2, 4, 8, 16, 32, 64, 128
CLKOUT
Note
1. When using an external clock source, leave XTALOUT floating.
Cypress Semiconductor Corporation • 198 Champion Court
Document Number: 38-07210 Rev. *G
• San Jose, CA 95134-1709 • 408-943-2600
Revised February 1, 2012
http://www.Datasheet4U.com






CY2077 Datasheet, Funktion
CY2077
Output Clock Switching Characteristics Commercial
Over the Operating Range[4]
Parameter
Description
Test Conditions
Min
t1w Output duty cycle at 1.4 V, 1 – 40 MHz, CL <= 50 pF
VDD = 4.5 – 5.5 V
40 – 125 MHz, CL <= 25 pF
t1w = t1A t1B
125 – 133 MHz, CL <= 15 pF
45
45
45
t1x Output duty cycle at VDD/2, 1 – 40 MHz, CL <= 50 pF
VDD = 4.5 – 5.5 V
40 – 125 MHz, CL <= 25 pF
t1x = t1A t1B
125 – 133 MHz, CL <= 15 pF
45
45
45
t1y Output duty cycle at VDD/2, 1 – 40 MHz, CL <= 30 pF
VDD = 3.0 – 3.6 V
40 – 100 MHz, CL <= 15 pF
t1y = t1A t1B
45
40
t2
Output clock rise time
Between 0.8 – 2.0 V, VDD = 4.5 V – 5.5 V, CL = 50 pF
Between 0.8 – 2.0 V, VDD = 4.5 V – 5.5 V, CL = 25 pF
Between 0.8 – 2.0 V, VDD = 4.5 V – 5.5 V, CL = 15 pF
Between 0.2 VDD – 0.8 VDD, VDD= 4.5 V – 5.5 V, CL = 50 pF –
Between 0.2 VDD – 0.8 VDD, VDD= 3.0 V – 3.6 V, CL = 30 pF –
Between 0.2 VDD – 0.8 VDD, VDD= 3.0 V – 3.6 V, CL = 15 pF –
t3 Output clock fall time Between 0.8 V –2.0 V, VDD = 4.5 V – 5.5 V, CL = 50 pF
Between 0.8 – 2.0 V, VDD = 4.5 V – 5.5 V, CL = 25 pF
Between 0.8 – 2.0 V, VDD = 4.5 V – 5.5 V, CL = 15 pF
Between 0.2 VDD – 0.8 VDD, VDD= 4.5 V – 5.5 V, CL = 50 pF –
Between 0.2 VDD – 0.8 VDD, VDD= 3.0 V – 3.6 V, CL = 30 pF –
Between 0.2 VDD – 0.8 VDD, VDD= 3.0 V – 3.6 V, CL = 15 pF –
t4 Startup time out of power PWR_DWN pin LOW to HIGH[5]
down
t5a Power down delay time PWR_DWN pin LOW to output LOW
(synchronous setting) (T= period of output CLK)
t5b Power down delay time PWR_DWN pin LOW to output LOW
(asynchronous setting)
t6 Power up time
From power on[5]
t7a Output disable time
OE pin LOW to output high-Z
(synchronous setting) (T= period of output CLK)
t7b Output disable time
OE pin LOW to output high-Z
(asynchronous setting)
t8 Output enable time
OE pin LOW to HIGH
(always synchronous
(T= period of output CLK)
enable)
t9 Peak-to-peak period jitter VDD = 3.0 V – 3.6 V, 4.5 V – 5.5 V, Fo > 33 MHz, VCO > 100 MHz –
VDD = 3.0 V – 5.5 V, Fo < 33 MHz
Typ Max Unit
– 55 %
– 55 %
– 55 %
– 55 %
– 55 %
– 55 %
– 55 %
– 60 %
– 1.8 ns
– 1.2 ns
– 0.9 ns
– 3.4 ns
– 4.0 ns
– 2.4 ns
– 1.8 ns
– 1.2 ns
– 0.9 ns
– 3.4 ns
– 4.0 ns
– 2.4 ns
1 2 ms
T/2 T + 10 ns
10 15 ns
1 2 ms
T/2 T + 10 ns
10 15 ns
T 1.5T+ ns
25ns
80 150 ps
0.3% 1% % of
FO
Notes
4. Not all parameters measured in production testing.
5. Oscillator start time can not be guaranteed for all crystal types. This specification is for operation with AT cut crystals with ESR < 70
Document Number: 38-07210 Rev. *G
Page 6 of 17
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6 Page









CY2077 pdf, datenblatt
Typical Jitter Trends for CY2077
Figure 12. Period Jitter (pk-pk) vs. VDD over Temperatures
Period Jitter (pk-pk) vs. VDDover Temperatures
(Fout=40MHz, Cload = 30pF)
100
80
60
40
20
0
2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0
VDD (V)
-40C
25C
85C
Figure 13. Period Jitter (pk-pk) vs. Output Frequency over Temperatures
Output Jitter (pk-pk) vs. Output Frequency
(VDD=3.3V, Cload=15pf, CMOS output)
100
80
60
40
20
0
0 20 40 60 80 100 120 140
Output frequency (MHz)
25C
-40C
85C
Output Jitter(pk-pk) vs. Output Frequency
(VDD=5.0V, Cload=15pf, CMOS output)
100
80
60
40
20
0
0 20 40 60 80 100 120 140
Output frequency (MHz)
25C
-40C
85C
CY2077
Document Number: 38-07210 Rev. *G
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