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AX2000 Schematic ( PDF Datasheet ) - Actel

Teilenummer AX2000
Beschreibung Axcelerator Family FPGAs
Hersteller Actel
Logo Actel Logo 




Gesamt 30 Seiten
AX2000 Datasheet, Funktion
Axcelerator Family FPGAs
v2.7
ue
Leading-Edge Performance
• 350+ MHz System Performance
• 500+ MHz Internal Performance
• High-Performance Embedded FIFOs
• 700 Mb/s LVDS Capable I/Os
Specifications
• Up to 2 Million Equivalent System Gates
• Up to 684 I/Os
• Up to 10,752 Dedicated Flip-Flops
• Up to 295 kbits Embedded SRAM/FIFO
• Manufactured on Advanced 0.15 μm CMOS Antifuse
Process Technology, 7 Layers of Metal
Features
• Single-Chip, Nonvolatile Solution
• Up to 100% Resource Utilization with 100% Pin Locking
• 1.5V Core Voltage for Low Power
• Footprint Compatible Packaging
• Flexible, Multi-Standard I/Os:
– 1.5V, 1.8V, 2.5V, 3.3V Mixed Voltage Operation
– Bank-Selectable I/Os – 8 Banks per Chip
– Single-Ended I/O Standards: LVTTL, LVCMOS, 3.3V
PCI, and 3.3V PCI-X
– Differential I/O Standards: LVPECL and LVDS
Table 1-1 • Axcelerator Family Product Profile
Device
Capacity (in Equivalent System Gates)
Typical Gates
Modules
Register (R-cells)
Combinatorial (C-cells)
Maximum Flip-Flops
Embedded RAM/FIFO
Number of Core RAM Blocks
Total Bits of Core RAM
Clocks (Segmentable)
Hardwired
Routed
PLLs
I/Os
I/O Banks
Maximum User I/Os
Maximum LVDS Channels
Total I/O Registers
Package
CSP
PQFP
BGA
FBGA
CQFP
CCGA
AX125
125,000
82,000
672
1,344
1,344
4
18,432
4
4
8
8
168
84
504
180
256, 324
– Voltage-Referenced I/O Standards: GTL+, HSTL
Class 1, SSTL2 Class 1 and 2, SSTL3 Class 1 and 2
– Registered I/Os
– Hot-Swap Compliant I/Os (except PCI)
– Programmable Slew Rate and Drive Strength on
Outputs
– Programmable Delay and Weak Pull-Up/Pull-Down
Circuits on Inputs
• Embedded Memory:
– Variable-Aspect 4,608-bit RAM Blocks (x1, x2, x4,
x9, x18, x36 Organizations Available)
– Independent, Width-Configurable Read and Write Ports
– Programmable Embedded FIFO Control Logic
• Segmentable Clock Resources
• Embedded Phase-Locked Loop:
– 14-200 MHz Input Range
– Frequency Synthesis Capabilities up to 1 GHz
• Deterministic, User-Controllable Timing
• Unique In-System Diagnostic and Debug Capability
with Actel Silicon Explorer II
• Boundary-Scan Testing Compliant with IEEE Standard
1149.1 (JTAG)
• FuseLockTM Secure Programming Technology
Prevents Reverse Engineering and Design Theft
AX250
250,000
154,000
1,408
2,816
2,816
12
55,296
4
4
8
8
248
124
744
208
256, 484
208, 352
AX500
500,000
286,000
2,688
5,376
5,376
16
73,728
4
4
8
8
336
168
1,008
AX1000
1,000,000
612,000
6,048
12,096
12,096
36
165,888
4
4
8
8
516
258
1,548
AX2000
2,000,000
1,060,000
10,752
21,504
21,504
64
294,912
4
4
8
8
684
342
2,052
208
484, 676
208, 352
729
484, 676, 896
352
624
896, 1152
352
624
November 2008
© 2008 Actel Corporation
i
*See Actel’s website for the latest version of the datasheet.
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AX2000 Datasheet, Funktion
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AX2000 pdf, datenblatt
Axcelerator Family FPGAs
Figure 1-8 • AX Routing Structures
operating with input frequencies ranging from 14 MHz
to 200 MHz and can generate output frequencies
between 20 MHz and 1 GHz. The clock can be either
divided or multiplied by factors ranging from 1 to 64.
Additionally, multiply and divide settings can be used in
any combination as long as the resulting clock frequency
is between 20 MHz and 1 GHz. Adjacent PLLs can be
cascaded to create complex frequency combinations.
The PLL can be used to introduce either a positive or a
negative clock delay of up to 3.75 ns in 250 ps
increments. The reference clock required to drive the PLL
can be derived from three sources: external input pad
(either single-ended or differential), internal logic, or the
output of an adjacent PLL.
Low Power (LP) Mode
The AX architecture was created for high-performance
designs but also includes a low power mode (activated via
the LP pin). When the low power mode is activated, I/O
banks can be disabled (inputs disabled, outputs tristated),
and PLLs can be placed in a power-down mode. All
internal register states are maintained in this mode.
Furthermore, individual I/O banks can be configured to
opt out of the LP mode, thereby giving the designer access
to critical signals while the rest of the chip is in low power
mode.
The power can be further reduced by providing an
external voltage source (VPUMP) to the device to bypass
the internal charge pump (See "Low Power Mode" on
page 2-89 for more information).
Design Environment
The Axcelerator family of FPGAs is fully supported by both
Actel's Libero™ Integrated Design Environment and
Designer FPGA Development software. Actel Libero IDE is
an integrated design manager that seamlessly integrates
design tools while guiding the user through the design
flow, managing all design and log files, and passing
necessary design data among tools. Additionally, Libero
IDE allows users to integrate both schematic and HDL
synthesis into a single flow and verify the entire design in
a single environment (see the Libero IDE Flow diagram
located on Actel’s website). Libero IDE includes Synplify®
Actel Edition (AE) from Synplicity®, ViewDraw® AE from
Mentor Graphics®, ModelSim® HDL Simulator from
Mentor Graphics, WaveFormer Lite™ AE from
SynaptiCAD®, and Designer software from Actel.
Actel's Designer software is a place-and-route tool and
provides a comprehensive suite of backend support tools
for FPGA development. The Designer software includes
the following:
• Timer – a world-class integrated static timing analyzer
and constraints editor which support timing-driven
place-and-route
• NetlistViewer – a design netlist schematic viewer
• ChipPlanner – a graphical floorplanner viewer and editor
• SmartPower – allows the designer to quickly estimate
the power consumption of a design
• PinEditor – a graphical application for editing pin
assignments and I/O attributes
• I/O Attribute Editor – displays all assigned and
unassigned I/O macros and their attributes in a
spreadsheet format
1-6 v2.7
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