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AMP374P6453BT1-C1S Schematic ( PDF Datasheet ) - AVED

Teilenummer AMP374P6453BT1-C1S
Beschreibung 64M X 72 SDRAM DIMM
Hersteller AVED
Logo AVED Logo 




Gesamt 12 Seiten
AMP374P6453BT1-C1S Datasheet, Funktion
AVED MEMORY PRODUCTS
Where Quality & Memory Merge
AMP374P6453BT1-C1H/S
64M X 72 SDRAM DIMM with ECC based on 32M X 8, 4 Banks, 8K REFRESH, 3.3V Synchronous DRAMs WITH SPD
DESCRIPTION
AVED Memory Products AMP374P6453BT1-C1H/S is a 64M bit X 72 Synchronous Dynamic RAM high density
memory module. The AVED Memory Products AMP374P6453BT1-C1H/S consists of eighteen CMOS 32M X 8 bit
with 4 banks Synchronous DRAMs in TSOP-II 400mil package and a 2K EEPROM in 8-pin TSSOP package on a
168-pin glass-epoxy substrate. Two 0.1uF decoupling capacitors are mounted on the printed circuit board in
parallel for each SDRAM.
The AVED Memory Products AMP374P6453BT1-C1H/S is a Dual In-Line Memory Module and is intended for mount-
ing into 168-pin edge connector sockets. Synchronous design allows precise cycle control with the use of system
clock. I/O transactions are possible on every clock cycle. Range of operating frequencies, programmable latencies
allows the same device to be useful for a variety of high bandwidth, high performance memory system applications.
APPLICATION
Main Memory unit for computer, Microcomputer memory,
Refresh memory for CRT.
FEATURES
Performance Ranges
Part Identification
- AMP374P6453BT1-C1H/S
8k cycles/64ms Ref, TSOP, Gold Contact Plating
- PC100 Compliant
Part #
Maximum Frequency/Speed
AMP374P6453BT1-C1H/S PC100MHz (10ns @ CL=2)
Burst Mode Operation
Auto & Self Refresh capability (8k cycles/64ms)
LVTTL compatible inputs and outputs
Single 3.3V ± 0.3V power supply
MRS cycle with address key programs
Latency (Access from column address)
Burst Length (1, 2, 4, 8 & Full Page)
Data Scramble (Sequential & Interleave)
All inputs are sampled at the positive
going edge of the system clock
Serial Presence Detect with EEPROM
PIN NAMES
Pin Nam e
A0 - A12
BA0 - BA1
DQ0 - DQ63
CB0 - 7
CLK0 - CLK3
CKE0 - CKE1
CS0 - CS3
RAS
CAS
WE
DQM0 - 7
VDD
Vss
*VREF
SDA
SCL
SA0 - 2
WP
DU
NC
Function
Address Input (multiplexed)
Select Bank
Data Input/Output
Check Bit (Data-in/out)
Clock Input
Clock Enable Input
Chip Select Input
Row Address Strobe
Column Address Strobe
W rite Enable
DQM
Power Supply(3.3V)
G ro u n d
Power Supply for Reference
Serial Address Data I/O
Serial Clock
Address in EEPROM
W rite Protect
Don’t Use
No Connection
Revision: 1.1
Revision Date: 11/2000
Document Number: 65830
Page Number: 1 of 12
http://www.Datasheet4U.com






AMP374P6453BT1-C1S Datasheet, Funktion
AVED MEMORY PRODUCTS
Where Quality & Memory Merge
AMP374P6453BT1-C1H/S
64M X 72 SDRAM DIMM with ECC based on 32M X 8, 4 Banks, 8K REFRESH, 3.3V Synchronous DRAMs WITH SPD
AC OPERATING TEST CONDITIONS ( VDD = 3.3V ± 0.3V, TA = 0 to 70ºC)
Parameter
AC input levels
Input timing measurement reference level
Input rise and fall time
Output measurement reference level
Output load condition
Value
VIH/VIL= 2.4V / 0.4V
1.4V
tr / tf = 1ns / 1ns
1.4V
See Fig. 2
OPERATING AC PARAMETER (AC operating conditions unless otherwise noted)
Refer to the individual component not the whole module.
Parameter
Row active to row active delay
RAS to CAS delay
Row precharge time
Row active time
Row cycle time
Last data in to row precharge
Last data in to active delay
Last data in to new col. add. delay
Last data in to burst stop
Column address to col. add. delay
Number of valid output data
Symbol
tRRD (min)
tRCD (min)
tRP (min)
tRAS (min)
tRAS (max)
tRC (min)
tRDL (min)
tDAL (min)
tCDL (min)
tBDL (min)
tCCD (min)
CAS latency = 2
Version
-1H
20
20
20
50
100
70
2
2CLK + 20 ns
1
1
1
1
Note : 1.
2.
3.
4.
5.
The minimum number of clock cycles is determined by dividing the minimum time
required with clock cycle time, and then rounding off to the next higher integer.
Minimum delay is required to complete write.
All parts allow every cycle column address change.
In case of row precharge interrupt, auto precharge and read burst stop.
For -80/1H/1L, tRDL=1CLK and tDAL=1CLK+20ns is also supported.
Unit
ns
ns
ns
ns
us
ns
CLK
-
CLK
CLK
CLK
ea
Note
1
1
1
1
1
2,5
5
2
2
3
4
Revision: 1.1
Revision Date: 11/2000
Document Number: 65830
Page Number: 6 of 12
http://www.Datasheet4U.com

6 Page









AMP374P6453BT1-C1S pdf, datenblatt
AVED MEMORY PRODUCTS
Where Quality & Memory Merge
AMP374P6453BT1-C1H/S
64M X 72 SDRAM DIMM with ECC based on 32M X 8, 4 Banks, 8K REFRESH, 3.3V Synchronous DRAMs WITH SPD
SERIAL PRESENCE DETECT
(CONTINUED FROM PRESIOUS PAGE)
Byte#
Function Description
62
63
64
65-71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100-103
104-130
131
132
SPD data revision code
Check sum for bytes 0-62
Manufacturer JEDEC ID code
Manufacturer JEDEC ID code
Manufacturing location
Manufacturer part #
Manufacturer part #
Manufacturer part #
Manufacturer part #
Manufacturer part #
Manufacturer part #
Manufacturer part #
Manufacturer part #
Manufacturer part #
Manufacturer part #
Manufacturer part #
Manufacturer part #
Manufacturer part #
Manufacturer part #
Manufacturer part #
Manufacturer part #
Manufacturer part #
Manufacturer part #
Manufacturer revision code (for PCB)
Manufacturer revision code (for component)
Manufacturer part #
Manufacturer part #
Manufacturer part #
Manufacturer revision code (for PCB)
Manufacturer revision code (for component)
Manufacturing date (Week)
Manufacturing date (Year)
Assembly serial #
Manufacturer specific data (for future use)
System frequency for 100MHz
PC100 specification details
133+ Unused storage locations
Function Supported
-1H
PC100 SPD Spec. Ver. 1.2A
-
AVED Memory Products
AVED Memory Products
Tustin
A
M
P
3
7
4
P
6
4
5
3
B
T
1
-
C
1
H
/
S
1
H
-
0
B-die (3RD Gen.)
-
-
-
Undefined
100MHz
Detailed 100MHz
information
Undefined
Hex Value
-1H
12h
4Ch
67h
00h
01h
41h
4Dh
50h
33h
37h
34h
50h
36h
34h
35h
33h
42h
54h
31h
2Dh
43h
31h
48h
2Fh
53h
31h
48h
20h
30h
42h
-
-
-
-
64h
FFh
-
Note
3
3
4
5
5
Notes:
1. The bank select address is excluded in counting the total # of Addresses.
2. This value is based on the component specification.
3. These bytes are programmed by code of Date, Week & Date, Year with BCD format.
4. These bytes are programmed by AVEDs own assembly serial # system. All modules may have different unique serial #s.
5. These bytes are Undefined and can be used for AVEDs own purpose.
Revision: 1.1
Revision Date: 11/2000
Document Number: 65830 Page Number: 12 of 12
http://www.Datasheet4U.com

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