Datenblatt-pdf.com


MX25U8035E Schematic ( PDF Datasheet ) - MACRONIX

Teilenummer MX25U8035E
Beschreibung FLASH MEMORY
Hersteller MACRONIX
Logo MACRONIX Logo 




Gesamt 30 Seiten
MX25U8035E Datasheet, Funktion
MX25U8035E
MX25U8035E DATASHEET
P/N: PM1654
REV. 1.4, NOV. 22, 2013
1
http://www.Datasheet4U.com






MX25U8035E Datasheet, Funktion
MX25U8035E
2.GENERAL DESCRIPTION
The MX25U8035E are 8,388,608 bit serial Flash memory, which is configured as 1,048,576 x 8 internally. When it is
in two or four I/O read mode, the structure becomes 4,194,304 bits x 2 or 2,097,152 bits x 4. MX25U8035E feature
a serial peripheral interface and software protocol allowing operation on a simple 3-wire bus while it is in single I/O
mode. The three bus signals are a clock input (SCLK), a serial data input (SI), and a serial data output (SO). Serial
access to the device is enabled by CS# input.
When it is in two I/O read mode, the SI pin and SO pin become SIO0 pin and SIO1 pin for address/dummy bits
input and data output. When it is in four I/O read mode, the SI pin, SO pin and WP# pin become SIO0 pin, SIO1
pin, SIO2 pin and SIO3 pin for address/dummy bits input and data output.
The MX25U8035E MXSMIO® (Serial Multi I/O) provides sequential read operation on whole chip.
After program/erase command is issued, auto program/ erase algorithms which program/ erase and verify the
specified page or sector/block locations will be executed. Program command is executed on byte basis, or page (256
bytes) basis, or word basis for erase command is executed on sector (4K-byte), block (32K-byte), or block (64K-byte),
or whole chip basis.
To provide user with ease of interface, a status register is included to indicate the status of the chip. The status read
command can be issued to detect completion status of a program or erase operation via WIP bit.
Advanced security features enhance the protection and security functions, please see security features section for
more details.
When the device is not in operation and CS# is high, it is put in standby mode.
The MX25U8035E utilizes Macronix's proprietary memory cell, which reliably stores memory contents even after
100,000 program and erase cycles.
Table 1. Additional Feature Comparison
Additional
Features
Protection and Security
Read Performance
SPI
QPI
Part
Name
Flexible Block
Protection
(BP0-BP3)
4K-bit security 1 I/O
OTP (104 MHz)
2 I/O
(84 MHz)
4 I/O
4 I/O
4 I/O
4 I/O
(84 MHz) (104 MHz) (84 MHz) (104 MHz)
MX25U8035E
V
V VVVVVV
Additional
Features
Identifier
Part
Name
RES
REMS
RDID
(command: (command: (command:
AB hex)
90 hex)
9F hex)
MX25U8035E
34 (hex)
C2 34 (hex)
(if ADD=0)
C2 25 34
QPIID
(Command:
AF hex)
C2 25 34
P/N: PM1654
REV. 1.4, NOV. 22, 2013
6
http://www.Datasheet4U.com

6 Page









MX25U8035E pdf, datenblatt
MX25U8035E
8.DEVICE OPERATION
1. Before a command is issued, status register should be checked to ensure device is ready for the intended
operation.
2. When incorrect command is inputted to this device, it enters standby mode and remains in standby mode until
next CS# falling edge. In standby mode, SO pin of the device is High-Z.
3. When correct command is inputted to this device, it enters active mode and remains in active mode until next
CS# rising edge.
4. Input data is latched on the rising edge of Serial Clock (SCLK) and data is shifted out on the falling edge of
SCLK. The difference of Serial mode 0 and mode 3 is shown as "Figure 1. Serial Modes Supported".
5. For the following instructions: RDID, RDSR, RDSCUR, READ, FAST_READ, RDSFDP, 2READ, 4READ, RES,
REMS, SQIID, RDBLOCK, the shifted-in instruction sequence is followed by a data-out sequence. After any bit
of data being shifted out, the CS# can be high. For the following instructions: WREN, WRDI, WRSR, SE, BE32K,
BE, CE, PP, 4PP, DP, ENSO, EXSO, WRSCUR, WPSEL, SBLK, SBULK, GBULK, SUSPEND, RESUME, NOP,
RSTEN, RST, EQIO, RSTQIO the CS# must go high exactly at the byte boundary; otherwise, the instruction will
be rejected and not executed.
6. While a Write Status Register, Program, or Erase operation is in progress, access to the memory array is
neglected and will not affect the current operation of Write Status Register, Program, Erase.
Figure 1. Serial Modes Supported
CPOL CPHA
(Serial mode 0) 0
0 SCLK
(Serial mode 3) 1
1 SCLK
SI
SO
shift in
MSB
shift out
MSB
Note:
CPOL indicates clock polarity of Serial master, CPOL=1 for SCLK high while idle, CPOL=0 for SCLK low while not
transmitting. CPHA indicates clock phase. The combination of CPOL bit and CPHA bit decides which Serial mode is
supported.
P/N: PM1654
12
REV. 1.4, NOV. 22, 2013
http://www.Datasheet4U.com

12 Page





SeitenGesamt 30 Seiten
PDF Download[ MX25U8035E Schematic.PDF ]

Link teilen




Besondere Datenblatt

TeilenummerBeschreibungHersteller
MX25U8035(MX25U4035 / MX25U8035) 4M-BIT [x 1/x 2/x 4] 1.8V CMOS SERIAL FLASHMacronix International
Macronix International
MX25U8035CMOS SERIAL FLASHMACRONIX
MACRONIX
MX25U8035EFLASH MEMORYMACRONIX
MACRONIX

TeilenummerBeschreibungHersteller
CD40175BC

Hex D-Type Flip-Flop / Quad D-Type Flip-Flop.

Fairchild Semiconductor
Fairchild Semiconductor
KTD1146

EPITAXIAL PLANAR NPN TRANSISTOR.

KEC
KEC


www.Datenblatt-PDF.com       |      2020       |      Kontakt     |      Suche