|
|
Teilenummer | MX25U1635E |
|
Beschreibung | FLASH MEMORY | |
Hersteller | MACRONIX | |
Logo | ||
Gesamt 30 Seiten MX25U1635E
MX25U1635E
DATASHEET
P/N: PM1472
REV. 1.9, NOV. 08, 2013
1
http://www.Datasheet4U.com
MX25U1635E
16M-BIT [x 1/x 2/x 4] 1.8V CMOS MXSMIO® (SERIAL MULTI I/O) FLASH MEMORY
1. FEATURES
GENERAL
• Serial Peripheral Interface compatible -- Mode 0 and Mode 3
• 16,777,216 x 1 bit structure or 8,388,608 x 2 bits (two I/O read mode) structure or 4,194,304 x 4 bits (four I/O
read mode) structure
• Equal Sectors with 4K byte each, or Equal Blocks with 32K byte each or Equal Blocks with 64K byte each
- Any Block can be erased individually
• Single Power Supply Operation
- 1.65 to 2.0 volt for read, erase, and program operations
• Latch-up protected to 100mA from -1V to Vcc +1V
• Low Vcc write inhibit is from 1.0V to 1.4V
PERFORMANCE
• High Performance
- Fast read for SPI mode
- 1 I/O: 104MHz with 8 dummy cycles
- 2 I/O: 84MHz with 4 dummy cycles, equivalent to 168MHz
- 4 I/O: 104MHz with 6 dummy cycles, equivalent to 416MHz
- Fast read for QPI mode
- 4 I/O: 84MHz with 4 dummy cycles, equivalent to 336MHz
- 4 I/O: 104MHz with 6 dummy cycles, equivalent to 416MHz
- Fast program time: 1.2ms(typ.) and 3ms(max.)/page (256-byte per page)
- Byte program time: 10us (typical)
- 8/16/32/64 byte Wrap-Around Burst Read Mode
- Fast erase time: 45ms (typ.)/sector (4K-byte per sector); 250ms(typ.) /block (32K-byte per block); 500ms(typ.) /
block (64K-byte per block); 9s(typ.) /chip
• Low Power Consumption
- Low active read current: 20mA(max.) at 104MHz, 15mA(max.) at 84MHz
- Low active erase/programming current: 20mA (typ.)
- Standby current: 25uA (typ.)
• Deep Power Down: 2uA(typ.)
• Typical 100,000 erase/program cycles
• 20 years data retention
SOFTWARE FEATURES
• Input Data Format
- 1-byte Command code
• Advanced Security Features
- Block lock protection
The BP0-BP3 status bit defines the size of the area to be software protection against program and erase
instructions
- Additional 4k-bit secured OTP for unique identifier
• Auto Erase and Auto Program Algorithm
- Automatically erases and verifies data at selected sector or block
P/N: PM1472
REV. 1.9, NOV. 08, 2013
6
http://www.Datasheet4U.com
6 Page MX25U1635E
6. DATA PROTECTION
During power transition, there may be some false system level signals which result in inadvertent erasure or
programming. The device is designed to protect itself from these accidental write cycles.
The state machine will be reset as standby mode automatically during power up. In addition, the control register
architecture of the device constrains that the memory contents can only be changed after specific command
sequences have completed successfully.
In the following, there are several features to protect the system from the accidental write cycles during VCC power-
up and power-down or from system noise.
• Power-on reset and tPUW: to avoid sudden power switch by system power supply transition, the power-on reset
and tPUW (internal timer) may protect the Flash.
• Valid command length checking: The command length will be checked whether it is at byte base and completed
on byte boundary.
• Write Enable (WREN) command: WREN command is required to set the Write Enable Latch bit (WEL) before
issung other commands to change data. The WEL bit will return to reset stage under following situation:
- Power-up
- Write Disable (WRDI) command completion
- Write Status Register (WRSR) command completion
- Page Program (PP) command completion
- Quad I/O Page Program (4PP) command completion
- Sector Erase (SE) command completion
- Block Erase 32KB (BE32K) command completion
- Block Erase (BE) command completion
- Chip Erase (CE) command completion
- Program/Erase Suspend
- Softreset command completion
- Write Security Register (WRSCUR) command completion
- Write Protection Selection (WPSEL) command completion
• Deep Power Down Mode: By entering deep power down mode, the flash device also is under protected from
writing all commands except Release from deep power down mode command (RDP) and Read Electronic
Signature command (RES) and softreset command.
• Advanced Security Features: there are some protection and security features which protect content from
inadvertent write and hostile access.
I. Block lock protection
- The Software Protected Mode (SPM) use (BP3, BP2, BP1, BP0) bits to allow part of memory to be protected
as read only. The protected area definition is shown as "Table 2. Protected Area Sizes", the protected areas are
more flexible which may protect various area by setting value of BP0-BP3 bits.
- The Hardware Proteced Mode (HPM) use WP#/SIO2 to protect the (BP3, BP2, BP1, BP0) bits and Status
Register Write Protect bit.
- In four I/O and QPI mode, the feature of HPM will be disabled.
P/N: PM1472
12
REV. 1.9, NOV. 08, 2013
http://www.Datasheet4U.com
12 Page | ||
Seiten | Gesamt 30 Seiten | |
PDF Download | [ MX25U1635E Schematic.PDF ] |
Teilenummer | Beschreibung | Hersteller |
MX25U1635E | FLASH MEMORY | MACRONIX |
Teilenummer | Beschreibung | Hersteller |
CD40175BC | Hex D-Type Flip-Flop / Quad D-Type Flip-Flop. |
Fairchild Semiconductor |
KTD1146 | EPITAXIAL PLANAR NPN TRANSISTOR. |
KEC |
www.Datenblatt-PDF.com | 2020 | Kontakt | Suche |