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PDF MX25U1001E Data sheet ( Hoja de datos )

Número de pieza MX25U1001E
Descripción FLASH MEMORY
Fabricantes MACRONIX 
Logotipo MACRONIX Logotipo



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No Preview Available ! MX25U1001E Hoja de datos, Descripción, Manual

ADVANCED INFORMATION
MX25U5121E
MX25U1001E
MX25U5121E, MX25U1001E
DATASHEET
P/N: PM1980
REV. 0.00, OCT. 11, 2013
1
http://www.Datasheet4U.com

1 page




MX25U1001E pdf
ADVANCED INFORMATION
MX25U5121E
MX25U1001E
program pulse widths (Any page to be programed should have page in the erased state first)
Status Register Feature
Electronic Identification
- JEDEC 1-byte manufacturer ID and 2-bytes device ID
HARDWARE FEATURES
SCLK Input
- Serial clock input
SI/SIO0
- Serial Data Input or Serial Data Input/Output for 2 x I/O read mode and 4 x I/O read mode
SO/SIO1
- Serial Data Output or Serial Data Input/Output for 2 x I/O read mode and 4 x I/O read mode
WP#/SIO2
- Hardware write protection or Serial Data Input/Output for 4 x I/O read mode
HOLD#/SIO3
- Pause the chip without diselecting the chip or Serial Data Input/Output for 4 x I/O read mode
• PACKAGE
- 8-pin SOP (150mil)
- 8-pin TSSOP (173mil)
- 8-USON (2x3mm)
- All devices are RoHS Compliant and Halogen-free
2. GENERAL DESCRIPTION
The device feature a serial peripheral interface and software protocol allowing operation on a simple 3-wire bus.
The three bus signals are a clock input (SCLK), a serial data input (SI), and a serial data output (SO). Serial access
to the device is enabled by CS# input.
The device provides sequential read operation on the whole chip.
After program/erase command is issued, auto program/erase algorithms which program/erase and verify the speci-
fied page or sector locations will be executed. Program command is executed on page (32 bytes) basis, and erase
command is executes on sector, or block, or whole chip.
To provide user with ease of interface, a status register is included to indicate the status of the chip. The status read
command can be issued to detect completion status of a program or erase operation via WIP bit.
When the device is not in operation and CS# is high, it is put in Standby Mode and draws less than 35uA (typical:25uA)
DC current.
The device utilizes Macronix proprietary memory cell, which reliably stores memory contents even after typical
100,000 program and erase cycles.
P/N: PM1980
REV. 0.00, OCT. 11, 2013
5
http://www.Datasheet4U.com

5 Page





MX25U1001E arduino
ADVANCED INFORMATION
MX25U5121E
MX25U1001E
9. DATA PROTECTION
During power transition, there may be some false system level signals which result in inadvertent erasure or
programming. The device is designed to protect itself from these accidental write cycles.
The state machine will be reset as standby mode automatically during power up. In addition, the control register
architecture of the device constrains that the memory contents can only be changed after specific command
sequences have completed successfully.
In the following, there are several features to protect the system from the accidental write cycles during VCC
powerup and power-down or from system noise.
• Valid command length checking: The command length will be checked whether it is at byte base and completed
on byte boundary.
• Write Enable (WREN) command: WREN command is required to set the Write Enable Latch bit (WEL) before
other command to change data. The WEL bit will return to reset stage under following situation:
- Power-up
- Write Disable (WRDI) command completion
- Write Status Register (WRSR) command completion
- Page Program (PP) command completion
- Sector Erase (SE) command completion
- Block Erase (BE) command completion
- Chip Erase (CE) command completion
Software Protection Mode (SPM): by using BP0-BP1 bits to set the part of Flash protected from data change.
Hardware Protection Mode (HPM): by using WP# going low to protect the BP0-BP1 bits and SRWD bit from data
change.
• Deep Power Down Mode: By entering Deep Power Down Mode, the flash device also is under protected from
writing all commands except Release from Deep Power Down Mode command (RDP).
Table 3. Protected Area Sizes
Status bit
BP1 BP0
00
01
10
11
MX25U5121E
0 (none)
1 (All)
2 (All)
3 (All)
Protect level
MX25U1001E
0 (none)
1 (1 block)
2 (All)
3 (All)
P/N: PM1980
11
REV. 0.00, OCT. 11, 2013
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