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CYD09S18V18 Schematic ( PDF Datasheet ) - Cypress Semiconductor

Teilenummer CYD09S18V18
Beschreibung Dual Port SRAM
Hersteller Cypress Semiconductor
Logo Cypress Semiconductor Logo 




Gesamt 30 Seiten
CYD09S18V18 Datasheet, Funktion
CYDXXS72V18
CYDXXS36V18
CYDXXS18V18
FullFlex™ Synchronous SDR
Dual Port SRAM
FullFlex™ Synchronous SDR Dual Port SRAM
Features
True dual port memory enables simultaneous access the
shared array from each port
Synchronous pipelined operation with single data rate (SDR)
operation on each port
SDR interface at 200 MHz
Up to 28.8 Gb/s bandwidth (200 MHz × 72-bit × 2 ports)
Selectable pipelined or flow-through mode
1.5 V or 1.8 V core power supply
Commercial and Industrial temperature
IEEE 1149.1 JTAG boundary scan
Available in 484-ball PBGA (× 72) and 256-ball FBGA (× 36
and × 18) packages
FullFlex72 family
36-Mbit: 512 K × 72 (CYD36S72V18)
18-Mbit: 256 K × 72 (CYD18S72V18)
9-Mbit: 128 K × 72 (CYD09S72V18)
FullFlex36 family
36-Mbit: 1 M × 36 (CYD36S36V18)
18-Mbit: 512 K × 36 (CYD18S36V18)
9-Mbit: 256 K × 36 (CYD09S36V18)
2-Mbit: 64 K × 36 (CYD02S36V18)
FullFlex18 family
36-Mbit: 2 M × 18 (CYD36S18V18)
18-Mbit: 1 M × 18 (CYD18S18V18)
9-Mbit: 512 K × 18 (CYD09S18V18)
Built in deterministic access control to manage address
collisions
Deterministic flag output upon collision detection
Collision detection on back-to-back clock cycles
First busy address readback
Advanced features for improved high speed data transfer and
flexibility
Variable impedance matching (VIM)
Echo clocks
Selectable LVTTL (3.3 V), Extended HSTL (1.4 V to 1.9 V),
1.8 V LVCMOS, or 2.5 V LVCMOS IO on each port
Burst counters for sequential memory access
Mailbox with interrupt flags for message passing
Dual chip enables for easy depth expansion
Functional Description
The FullFlex™ dual port SRAM families consist of 2-Mbit, 9-Mbit,
18-Mbit, and 36-Mbit synchronous, true dual port static RAMs
that are high speed, low power 1.8 V or 1.5 V CMOS. Two ports
are provided, enabling simultaneous access to the array.
Simultaneous access to a location triggers deterministic access
control. For FullFlex72 these ports operate independently with
72-bit bus widths and each port is independently configured for
two pipelined stages. Each port is also configured to operate in
pipelined or flow through mode.
The advanced features include the following:
Built in deterministic access control to manage address
collisions during simultaneous access to the same memory
location
Variable impedance matching (VIM) to improve data
transmission by matching the output driver impedance to the
line impedance
Echo clocks to improve data transfer
To reduce the static power consumption, chip enables power
down the internal circuitry. The number of latency cycles before
a change in CE0 or CE1 enables or disables the databus
matches the number of cycles of read latency selected for the
device. For a valid write or read to occur, activate both chip
enable inputs on a port.
Each port contains an optional burst counter on the input address
register. After externally loading the counter with the initial
address, the counter increments the address internally.
Additional device features include a mask register and a mirror
register to control counter increments and wrap around. The
counter interrupt (CNTINT) flags notify the host that the counter
reaches maximum count value on the next clock cycle. The host
reads the burst counter internal address, mask register address,
and busy address on the address lines. The host also loads the
counter with the address stored in the mirror register by using the
retransmit functionality. Mailbox interrupt flags are used for
message passing, and JTAG boundary scan and asynchronous
Master Reset (MRST) are also available. The Logic Block
Diagram on page 2 shows these features.
The FullFlex72 is offered in a 484-ball plastic BGA package. The
FullFlex36 and FullFlex18 are available in 256-ball fine pitch
BGA package except the 36-Mbit devices which are offered in
484-ball plastic BGA package.
Cypress Semiconductor Corporation • 198 Champion Court
Document Number: 38-06082 Rev. *O
• San Jose, CA 95134-1709 • 408-943-2600
Revised February 5, 2013
http://www.Datasheet4U.com






CYD09S18V18 Datasheet, Funktion
CYDXXS72V18
CYDXXS36V18
CYDXXS18V18
Figure 3. FullFlex18 SDR 484-ball BGA Pinout (Top View)[11]
12
3
45678
9
10 11 12 13
14 15 16 17 18 19 20 21 22
A DNU DNU DNU DNU DNU DNU DNU DNU DQ15L DQ12L DQ9L DQ9R DQ12R DQ15R DNU DNU DNU DNU DNU DNU DNU DNU
B DNU DNU DNU DNU DNU DNU DNU DNU DQ16L DQ13L DQ10L DQ10R DQ13R DQ16R DNU DNU DNU DNU DNU DNU DNU DNU
C DNU DNU
D DNU DNU
VSS
VSS
VSS
VSS
DNU
VSS
DNU DNU
CQ1L CQ1L
DNU
VSS
DQ17L DQ14L DQ11L DQ11R DQ14R DQ17R
LOWSPDL PORTSTD0L ZQ0L[12] BUSYL CNTINTL PORTSTD1L
DNU
DNU
DNU DNU
CQ1R CQ1R
DNU
VSS
VSS
VSS
VSS
VSS
DNU DNU
DNU DNU
E DNU DNU VDDIOL VSS VSS VDDIOL VDDIOR VDDIOR VDDIOR VDDIOR VTTL VTTL VTTL VDDIOL VDDIOL VDDIOL VDDIOL DNU VSS VDDIOR DNU DNU
F DNU DNU CE1L CE0L VDDIOL VDDIOL VDDIOR VDDIOR VDDIOR VCORE VCORE VCORE VCORE VDDIOL VDDIOL VDDIOL VDDIOR VDDIOR CE0R CE1R DNU DNU
G A0L A1L RETL BE1L VDDIOL VDDIOL VREFL VSS
VSS
VSS
VSS VSS
VSS
VSS
VSS VREFR VDDIOR VDDIOR BE1R RETR A1R A0R
H A2L A3L WRPL DNU VDDIOL VDDIOL VSS VSS
VSS
VSS
VSS VSS
VSS
VSS
VSS VSS VDDIOR VDDIOR DNU WRPR A3R A2R
J A4L A5L READYL
K A6L A7L ZQ1L[12]
DNU VDDIOL VDDIOL
DNU VTTL VCORE
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VDDIOR VDDIOR DNU
VCORE VDDIOR DNU
READYR A5R A4R
ZQ1R[12] A7R A6R
L A8L A9L CL
OEL VTTL VCORE VSS VSS
VSS
VSS
VSS VSS
VSS
VSS
VSS VSS VCORE VTTL OER
CR A9R A8R
M A10L A11L VSS
DNU VTTL VCORE VSS VSS
VSS
VSS
VSS VSS
VSS
VSS
VSS VSS VCORE VTTL DNU
VSS A11R A10R
N A12L A13L ADSL DNU VDDIOL VCORE VSS VSS
VSS
VSS
VSS VSS
VSS
VSS
VSS VSS VCORE VTTL DNU ADSR A13R A12R
P A14L A15L CNT/MSKL DNU VDDIOL VDDIOL VSS VSS
VSS
VSS
VSS VSS
VSS
VSS
VSS VSS VDDIOR VDDIOR DNU CNT/MSKR A15R A14R
R A16L A17L CNTENL BE0L VDDIOL VDDIOL VSS VSS
VSS
VSS
VSS VSS
VSS
VSS
VSS VSS VDDIOR VDDIOR BE0R CNTENR A17R A16R
T A18L A19L CNTRSTL INTL VDDIOL VDDIOL VREFL VSS
VSS
VSS
VSS VSS
VSS
VSS
VSS VREFR VDDIOR VDDIOR INTR CNTRSTR A19R A18R
U A20L DNU R/WL CQENL VDDIOL VDDIOL VDDIOR VDDIOR VDDIOR VCORE VCORE VCORE VCORE VDDIOL VDDIOL VDDIOL VDDIOR VDDIOR CQENR R/WR DNU A20R
V DNU DNU FTSELL VDDIOL DNU VDDIOR VDDIOR VDDIOR VDDIOR VTTL VTTL VTTL VDDIOL VDDIOL VDDIOL VDDIOL VDDIOR TRST VDDIOR FTSELR DNU DNU
W DNU DNU VSS
MRST VSS CQ0L CQ0L DNU PORTSTD1R CNTINTR BUSYR ZQ0R[12] PORTSTD0R LOWSPDR VSS CQ0R CQ0R VSS
TDI
TDO DNU DNU
Y DNU DNU VSS
VSS DNU DNU DNU DNU DQ8L DQ5L DQ2L DQ2R DQ5R DQ8R DNU DNU DNU DNU TMS
TCK DNU DNU
AA DNU DNU DNU DNU DNU DNU DNU DNU DQ7L DQ4L DQ1L DQ1R DQ4R DQ7R DNU DNU DNU DNU DNU DNU DNU DNU
AB DNU DNU DNU DNU DNU DNU DNU DNU DQ6L DQ3L DQ0L DQ0R DQ3R DQ6R DNU DNU DNU DNU DNU DNU DNU DNU
Notes
11. Use this pinout only for device CYD36S18V18 of the FullFlex18 family.
12. Leave this ball unconnected to disable VIM.
Document Number: 38-06082 Rev. *O
Page 6 of 53

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CYD09S18V18 pdf, datenblatt
CYDXXS72V18
CYDXXS36V18
CYDXXS18V18
address matches enable to generate the BUSY flag. However,
none of the addresses are saved into the busy address register.
When a busy readback is performed, the address of the first
match that happens at least two clocks cycles after the busy
readback is saved into the busy address register.
Table 3. tCCS Timing for All Operating Modes
Port A—Early Arriving Port Port B—Late Arriving Port
Mode
Active Edge
Mode
Active Edge
SDR C SDR
C
tCCS
Unit
C Rise to Opposite C Rise Setup Time for Non Corrupt Data
tCYC(min) – 0.5
ns
Table 4. Deterministic Access Control Logic
Left Port
Read
Write
Right Port
Read
Read
Left Clock
X
> tCCS
0
< tCCS
Right Clock
X
0
> tCCS
0
0 < tCCS
Read
Write
> tCCS
0
< tCCS
0
> tCCS
0
0 < tCCS
Write
Write
0
0
> tCCS
> –tCCS & < tCCS
> tCCS
0
BUSYL
H
H
H
H
H
H
H
H
H
H
L
H
L
L
L
H
BUSYR
H
H
H
H
L
H
L
H
H
H
H
H
H
L
H
L
Description
No collision
Read OLD data
Read NEW data
Read OLD data
Data not guaranteed
Read NEW data
Data Not guaranteed
Read NEW data
Read OLD data
Read NEW data
Data Not guaranteed
Read OLD data
Data not guaranteed
Array data corrupted
Array stores right port data
Array stores left port data
Variable Impedance Matching
Each port contains a variable impedance matching circuit to set
the impedance of the IO driver to match the impedance of the
on-board traces. The impedance is set for all outputs except
JTAG and is done by port. To take advantage of the VIM feature,
connect a calibrating resistor (RQ) that is five times the value of
the intended line impedance from the ZQ[1:0][27] pin to VSS. The
output impedance is then adjusted to account for drifts in supply
voltage and temperature every 1024 clock cycles. If a port’s clock
is suspended, the VIM circuit retains its last setting until the clock
is restarted. On restart, it then resumes periodic adjustment. In
the case of a significant change in device temperature or supply
voltage, recalibration happens every 1024 clock cycles. A master
reset initializes the VIM circuitry. Table 5 shows the VIM
parameters and Table 6 describes the VIM operation modes.
To disable VIM, connect the ZQ pin to VDDIO of the relative
supply for the IOs before a Master Reset.
Table 5. Variable Impedance Matching Parameters
Parameter
RQ value
Output impedance
Reset time
Update time
Min Max Unit
100 275
20 55
– 1024 Cycles
– 1024 Cycles
Tolerance
±2%
±15%
Table 6. Variable Impedance Matching Operation
RQ Connection
Output Configuration
100 –275 to VSS Output driver impedance = RQ/5 ± 15%
at Vout = VDDIO/2
ZQto VDDIO
VIM disabled. Rout < 20 at Vout =
VDDIO/2
Note
27. The pin ZQ[1] is applicable only for 36 Mbit devices. This pin is DNU for 18 Mbit and lower density devices.
Document Number: 38-06082 Rev. *O
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