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Teilenummer | D720112GK |
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Beschreibung | UPD720112 | |
Hersteller | NEC | |
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Gesamt 30 Seiten DATA SHEET
MOS INTEGRATED CIRCUIT
µPD720112
USB 2.0 HUB CONTROLLER
The µPD720112 is a USB 2.0 hub device that complies with the Universal Serial Bus (USB) Specification Revision
2.0 and works up to 480 Mbps. USB 2.0 compliant transceivers are integrated for upstream and all downstream ports.
The µPD720112 works backward compatible either when any one of the downstream ports is connected to a USB 1.1
compliant device, or when the upstream port is connected to a USB 1.1 compliant host.
Detailed function descriptions are provided in the following user’s manual. Be sure to read the manual before designing.
µPD720112 User’s Manual: S16617E
FEATURES
• Compliant with Universal Serial Bus Specification Revision 2.0 (Data Rate 1.5/12/480 Mbps)
• Certified by USB implementers forum and granted the USB 2.0 high-speed Logo
• High-speed or full-speed packet protocol sequencer for Endpoint 0/1
• 4 (Max.) downstream facing ports
• All downstream facing ports can handle high-speed (480 Mbps), full-speed (12 Mbps), and low-speed (1.5
Mbps) transaction.
• Supports split transaction to handle full-speed and low-speed transaction on downstream facing ports when
Hub controller is working in high-speed mode.
• One Transaction Translator per Hub and supports four non-periodic buffers
• Supports self-powered and bus-powered mode
• Supports Over-current detection and Individual or ganged power control
• Supports configurable vendor ID, product ID, string descriptors and others with external Serial ROM
• Supports “non-removable” attribution on individual port
• Uses 30 MHz X’tal, or clock input
• Supports downstream port status with LED
• 2.5 V and 3.3 V power supplies
The information in this document is subject to change without notice. Before using this document, please
confirm that this is the latest version.
Not all products and/or types are available in every country. Please check with an NEC Electronics
sales representative for availability and additional information.
Document No. S16616EJ2V0DS00 (2nd edition)
Date Published September 2004 NS CP (N)
Printed in Japan
2004
Free Datasheet http://www.Datasheet4U.com
µPD720112
1. PIN INFORMATION
Pin Name
X1_CLK
X2
SYSRSTB
RPU
DP(4:1)
DM(4:1)
DPU
DMU
BUS_SELF
LPWRM
RREF
CSB(4:1)
PPB(4:1)
VBUSM
SCL
SDA/GANG_B
EXROM_EN
AMBER
GREEN
LED(4:1)
TEST
SCAN_MODE
VDD33
VDD25
AVDD
VSS
AVSS
AVSS(R)
I/O Buffer Type
I
O
I
A (O)
I/O
I/O
I/O
I/O
I
I
A (O)
I
O
I
O
I/O
2.5 V input
2.5 V output
5 V tolerant Schmitt input
USB pull-up control
USB D+ signal I/O
USB D− signal I/O
USB D+ signal I/O
USB D− signal I/O
3.3 V Schmitt input
3.3 V Schmitt input
Analog
5 V tolerant input
5 V tolerant N-ch open drain
5 V tolerant Schmitt input
3.3 V output
3.3 V Schmitt I/O
I 3.3 V Schmitt input
O 5 V tolerant output
O 5 V tolerant output
O 5 V tolerant output
I 3.3 V input
I 3.3 V input
Active
Level
Low
Low
Low
Low
Function
Crystal oscillator in or clock input
Oscillator out
Asynchronous chip reset
External 1.5 kΩ pull-up resistor control
USB’s downstream facing port D+ signal
USB’s downstream facing port D− signal
USB’s upstream facing port D+ signal
USB’s upstream facing port D− signal
Power mode select
Local power monitor
Reference resistor
Port’s over-current status input
Port’s power supply control output
VBUS monitor
External serial ROM clock out
External serial ROM data IO or power
management mode select
External serial ROM input enable
Amber colored LED control output
Green colored LED control output
LED indicator output for downstream port status
Test signal
Test signal
3.3 V VDD
2.5 V VDD
2.5 V VDD for analog circuit
VSS
VSS for analog circuit
VSS for reference resistor. Connect to AVSS.
Remark “5 V tolerant“ means that the buffer is 3 V buffer with 5 V tolerant circuit.
6 Data Sheet S16616EJ2V0DS
Free Datasheet http://www.Datasheet4U.com
6 Page USB Interface Block
Parameter
Output pin impedance
Bus pull-up resistor on upstream facing
port
Bus pull-up resistor on downstream
facing port
Termination voltage for upstream facing
port pullup (full-speed)
Input Levels for Low-/full-speed:
High-level input voltage (drive)
High-level input voltage (floating)
Low-level input voltage
Differential input sensitivity
Differential common mode range
Output Levels for Low-/full-speed:
High-level output voltage
Low-level output voltage
SE1
Output signal crossover point voltage
Input Levels for High-speed:
High-speed squelch detection threshold
(differential signal)
High-speed disconnect detection
threshold (differential signal)
High-speed data signaling common
mode voltage range
High-speed differential input signaling
levels
Output Levels for High-speed:
High-speed idle state
High-speed data signaling high
High-speed data signaling low
Chirp J level (different signal)
Chirp K level (different signal)
Symbol
ZHSDRV
RPU
Conditions
Includes RS resistor
RPD
VTERM
VIH
VIHZ
VIL
VDI (D+) − (D−)
VCM Includes VDI range
VOH
VOL
VOSE1
VCRS
RL of 14.25 kΩ to GND
RL of 1.425 kΩ to 3.6 V
VHSSQ
VHSDSC
VHSCM
See Figure 2-4.
VHSOI
VHSOH
VHSOL
VCHIRPJ
VCHIRPK
µPD720112
MIN
40.5
1.425
14.25
3.0
MAX
49.5
1.575
15.75
3.6
Unit
Ω
kΩ
kΩ
V
2.0 V
2.7 3.6 V
0.8 V
0.2 V
0.8 2.5 V
2.8 3.6 V
0.0 0.3 V
0.8 V
1.3 2.0 V
100 150 mV
525 625 mV
−50
+500
mV
−10.0
360
−10.0
700
−900
+10
440
+10
1100
−500
mV
mV
mV
mV
mV
12 Data Sheet S16616EJ2V0DS
Free Datasheet http://www.Datasheet4U.com
12 Page | ||
Seiten | Gesamt 30 Seiten | |
PDF Download | [ D720112GK Schematic.PDF ] |
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