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39VF400A Schematic ( PDF Datasheet ) - Silicon Storage Technology

Teilenummer 39VF400A
Beschreibung SST39VF400A
Hersteller Silicon Storage Technology
Logo Silicon Storage Technology Logo 




Gesamt 30 Seiten
39VF400A Datasheet, Funktion
2 Mbit / 4 Mbit / 8 Mbit (x16) Multi-Purpose Flash
SST39LF200A / SST39LF400A / SST39LF800A
SST39VF200A / SST39VF400A / SST39VF800A
SST39LF/VF200A / 400A / 800A3.0 & 2.7V 2Mb / 4Mb / 8Mb (x16) MPF memories
FEATURES:
Data Sheet
• Organized as 128K x16 / 256K x16 / 512K x16
• Single Voltage Read and Write Operations
– 3.0-3.6V for SST39LF200A/400A/800A
– 2.7-3.6V for SST39VF200A/400A/800A
Superior Reliability
Endurance: 100,000 Cycles (typical)
Greater than 100 years Data Retention
Low Power Consumption
Active Current: 20 mA (typical)
Standby Current: 3 µA (typical)
Sector-Erase Capability
Uniform 2 KWord sectors
Block-Erase Capability
Uniform 32 KWord blocks
Fast Read Access Time
45 and 55 ns for SST39LF200A/400A
55 ns for SST39LF800A
70 and 90 ns for SST39VF200A/400A/800A
Latched Address and Data
Fast Erase and Word-Program
Sector-Erase Time: 18 ms (typical)
Block-Erase Time: 18 ms (typical)
Chip-Erase Time: 70 ms (typical)
Word-Program Time: 14 µs (typical)
Chip Rewrite Time:
2 seconds (typical) for SST39LF/VF200A
4 seconds (typical) for SST39LF/VF400A
8 seconds (typical) for SST39LF/VF800A
Automatic Write Timing
Internal VPP Generation
End-of-Write Detection
Toggle Bit
Data# Polling
CMOS I/O Compatibility
JEDEC Standard
Flash EEPROM Pinouts and command sets
Packages Available
48-lead TSOP (12mm x 20mm)
48-ball TFBGA (6mm x 8mm)
PRODUCT DESCRIPTION
The SST39LF200A/400A/800A and SST39VF200A/400A/
800A devices are 128K x16 / 256K x16 / 512K x16 CMOS
Multi-Purpose Flash (MPF) manufactured with SSTs pro-
prietary, high performance CMOS SuperFlash technology.
The split-gate cell design and thick oxide tunneling injector
attain better reliability and manufacturability compared with
alternate approaches. The SST39LF200A/400A/800A
write (Program or Erase) with a 3.0-3.6V power supply. The
SST39VF200A/400A/800A write (Program or Erase) with a
2.7-3.6V power supply. These devices conform to JEDEC
standard pinouts for x16 memories.
Featuring high performance Word-Program, the
SST39LF200A/400A/800A and SST39VF200A/400A/
800A devices provide a typical Word-Program time of 14
µsec. The devices use Toggle Bit or Data# Polling to detect
the completion of the Program or Erase operation. To pro-
tect against inadvertent write, they have on-chip hardware
and software data protection schemes. Designed, manu-
factured, and tested for a wide spectrum of applications,
these devices are offered with a guaranteed endurance of
10,000 cycles. Data retention is rated at greater than 100
years.
The SST39LF200A/400A/800A and SST39VF200A/400A/
800A devices are suited for applications that require conve-
nient and economical updating of program, configuration,
or data memory. For all system applications, they signifi-
cantly improve performance and reliability, while lowering
power consumption. They inherently use less energy dur-
ing Erase and Program than alternative flash technologies.
When programming a flash device, the total energy con-
sumed is a function of the applied voltage, current, and
time of application. Since for any given voltage range, the
SuperFlash technology uses less current to program and
has a shorter erase time, the total energy consumed during
any Erase or Program operation is less than alternative
flash technologies. These devices also improve flexibility
while lowering the cost for program, data, and configuration
storage applications.
The SuperFlash technology provides fixed Erase and Pro-
gram times, independent of the number of Erase/Program
cycles that have occurred. Therefore the system software
or hardware does not have to be modified or de-rated as is
necessary with alternative flash technologies, whose Erase
and Program times increase with accumulated Erase/Pro-
gram cycles.
To meet surface mount requirements, the SST39LF200A/
400A/800A and SST39VF200A/400A/800A are offered in
both 48-lead TSOP packages and 48-ball TFBGA pack-
ages. See Figures 1 and 2 for pinouts.
©2001 Silicon Storage Technology, Inc.
S71117-04-000 6/01
360
1
The SST logo and SuperFlash are registered trademarks of Silicon Storage Technology, Inc.
MPF is a trademark of Silicon Storage Technology, Inc.
These specifications are subject to change without notice.
Free Datasheet http://www.Datasheet4U.com






39VF400A Datasheet, Funktion
2 Mbit / 4 Mbit / 8 Mbit Multi-Purpose Flash
SST39LF200A / SST39LF400A / SST39LF800A
SST39VF200A / SST39VF400A / SST39VF800A
Data Sheet
TOP VIEW (balls facing down)
SST39LF/VF200A
6 A13 A12 A14 A15 A16 NC DQ15 VSS
5 A9 A8 A10 A11 DQ7 DQ14 DQ13 DQ6
4
WE# NC NC NC DQ5 DQ12 VDD DQ4
3
NC NC NC NC DQ2 DQ10 DQ11 DQ3
2
A7 NC A6 A5 DQ0 DQ8 DQ9 DQ1
1
A3 A4 A2 A1 A0 CE# OE# VSS
ABCDEFGH
TOP VIEW (balls facing down)
SST39LF/VF400A
6 A13 A12 A14 A15 A16 NC DQ15 VSS
5 A9 A8 A10 A11 DQ7 DQ14 DQ13 DQ6
4 WE# NC NC NC DQ5 DQ12 VDD DQ4
3
NC NC NC NC DQ2 DQ10 DQ11 DQ3
2
A7 A17 A6 A5 DQ0 DQ8 DQ9 DQ1
1
A3 A4 A2 A1 A0 CE# OE# VSS
ABCDEFGH
TOP VIEW (balls facing down)
SST39LF/VF800A
6 A13 A12 A14 A15 A16 NC DQ15 VSS
5 A9 A8 A10 A11 DQ7 DQ14 DQ13 DQ6
4 WE# NC NC NC DQ5 DQ12 VDD DQ4
3
NC NC A18 NC DQ2 DQ10 DQ11 DQ3
2
A7 A17 A6 A5 DQ0 DQ8 DQ9 DQ1
1
A3 A4 A2 A1 A0 CE# OE# VSS
ABCDEFGH
FIGURE 2: PIN ASSIGNMENTS FOR 48-BALL TFBGA
©2001 Silicon Storage Technology, Inc.
6
S71117-04-000 6/01 360
Free Datasheet http://www.Datasheet4U.com

6 Page









39VF400A pdf, datenblatt
2 Mbit / 4 Mbit / 8 Mbit Multi-Purpose Flash
SST39LF200A / SST39LF400A / SST39LF800A
SST39VF200A / SST39VF400A / SST39VF800A
Data Sheet
TABLE 10: DC OPERATING CHARACTERISTICS
VDD = 3.0-3.6V FOR SST39LF200A/400A/800A AND 2.7-3.6V FOR SST39VF200A/400A/800A
Limits
Symbol Parameter
Min Max Units Test Conditions
IDD
ISB
ILI
ILO
VIL
VIH
VIHC
VOL
VOH
Power Supply Current
Read
Program and Erase
Standby VDD Current
Input Leakage Current
Output Leakage Current
Input Low Voltage
Input High Voltage
Input High Voltage (CMOS)
Output Low Voltage
Output High Voltage
0.7VDD
VDD-0.3
VDD-0.2
30
30
20
1
10
0.8
0.2
Address input = VIL/VIH, at f=1/TRC Min.,
VDD=VDD Max.
mA CE#=OE#=VIL,WE#=VIH, all I/Os open
mA CE#=WE#=VIL, OE#=VIH
µA CE#=VIHC, VDD = VDD Max.
µA VIN =GND to VDD, VDD = VDD Max.
µA VOUT =GND to VDD, VDD = VDD Max.
VDD = VDD Min.
V VDD = VDD Max.
V VDD = VDD Max.
V IOL = 100 µA, VDD = VDD Min.
V IOH = -100 µA, VDD = VDD Min.
T10.5 360
TABLE 11: RECOMMENDED SYSTEM POWER-UP TIMINGS
Symbol
Parameter
Minimum
Units
TPU-READ1
Power-up to Read Operation
100 µs
TPU-WRITE1
Power-up to Program/Erase Operation
100 µs
T11.0 360
1. This parameter is measured only for initial qualification and after a design or process change that could affect this parameter.
TABLE 12: CAPACITANCE (Ta = 25°C, f=1 Mhz, other pins open)
Parameter
Description
Test Condition
Maximum
CI/O1
CIN1
I/O Pin Capacitance
Input Capacitance
VI/O = 0V
VIN = 0V
12 pF
6 pF
T12.0 360
1. This parameter is measured only for initial qualification and after a design or process change that could affect this parameter.
TABLE 13: RELIABILITY CHARACTERISTICS
Symbol
Parameter
Minimum Specification Units Test Method
NEND1
Endurance
10,000
Cycles JEDEC Standard A117
TDR1
Data Retention
100 Years JEDEC Standard A103
ILTH1
Latch Up
100 + IDD
mA JEDEC Standard 78
T13.1 360
1. This parameter is measured only for initial qualification and after a design or process change that could affect this parameter.
©2001 Silicon Storage Technology, Inc.
12
S71117-04-000 6/01 360
Free Datasheet http://www.Datasheet4U.com

12 Page





SeitenGesamt 30 Seiten
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