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AL1101 Schematic ( PDF Datasheet ) - Wavefront

Teilenummer AL1101
Beschreibung 24-Bit Analog-to-Digital Converter
Hersteller Wavefront
Logo Wavefront Logo 




Gesamt 8 Seiten
AL1101 Datasheet, Funktion
AL1101
24-Bit Analog-to-Digital Converter
General Description
The AL1101 is a 24-bit sigma-delta
stereo analog-to-digital audio converter
using Wavefront’s ClockEZ™ technology.
With dynamic range of 107dB, simplified
interface, and low power consumption,
the AL1101 (and its companion AL1201
DAC) is a best-in-class solution for
44.1kHz and 48kHz operation.
Applications
Digital Mixing Boards
Signal Processors
Digital Effects Boxes
Digital Recorders
Computer Sound Boards
Karaoke Systems
Car Audio Systems
Features
24-bit conversion
107dB dynamic range (A-wt)
0.002% THD (input = -1dBFS)
ClockEZ™ circuitry: internal PLL derives all
necessary timing signals from one external
Fs clock
64X oversampling, 5th order 1-bit   -
¡
modulator
64:1 linear-phase digital decimation filter
Sample rate: 24kHz to 55kHz
Digital high-pass filter
Low power: 110mW (Fs = 48kHz)
Serial output selectable: 32/24 bits/frame
Full scale differential input = ±4V
5V operation
Architecture Block diagram and Package
INL+
INR+
INL-
INR-
AGND
MID
REF+
VA
REF-
AGND
VD DGND
DGND
DOUT
FORMAT
WDCLK
16 pin SOIC
150 mils wide
Wavefront Semiconductor 200 Scenic View Drive Cumberland, RI 02864 U.S.A.
Tel: +1 401 658-3670 Fax: +1 401 658-3680 Email: [email protected]
On the web at www.wavefrontsemi.com
1
AL1101-0305
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AL1101 Datasheet, Funktion
Digital High Pass Output Filter
The AL1101 has an internal 2.5Hz single pole digital filter, which removes any offset present in
the internal amplifiers and prevents DC codes from appearing at the data outputs. The response
of the filter is -0.067dB at 20Hz.
Clock Generator and PLL
The AL1101 contains an internal PLL that locks to the rising edge of WDCLK and produces all
necessary high frequency clocks and timing signals to operate the device. This high quality PLL
will reject any high-frequency jitter on the incoming wordclock (jitter rejection corner at
approximately 4kHz).
The PLL allows a simplified user interface and eliminates the need of running high frequency
clocks to the part on PCB traces. This reduces unwanted RF noise and coupling problems that
can occur when such clock signals are required on input pins for a device.
Reference and MID
The differential potential between the REF+ and REF- pins (connected to +5V and GND
respectively) determines the amount of charge that is added to or removed from the modulator’s
first stage during each input sample period (64*Fs). It is very important that REF+ is well
bypassed to REF- (0.1µF ceramic capacitor as close as possible to the pins) to remove the
unwanted effects of high frequency noise.
The MID potential is developed on-chip (VA/2 Volts) and is used to bias the internal amplifiers in
the modulator, and to provide the reference point which determines the polarity of the modulator
output. It requires a 0.1µF bypass capacitor to GND at the pin. No load current should be
taken from the MID pin.
Power Supplies and Ground
A single low-impedance +5V supply is all that is required to achieve the specified performance.
A +5V supply plane on the PCB is recommended if possible. VA and VD may be directly
connected to +5V, and REF+ should be isolated with a 1kresistor to +5V.
A single low impedance ground plane can be used for all GND connections, simplifying PCB
layout. Each supply pin should be bypassed to GND with a 0.1µF ceramic capacitor positioned
as close to the pins as possible.
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