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Teilenummer | QN8075 |
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Beschreibung | Single-Chip Low-Power FM Receiver | |
Hersteller | Quintic | |
Logo | ||
Gesamt 19 Seiten QN8075
Single-Chip Low-Power FM Receiver for Portable Devices
__________________________ General Description __________________________
The QN8075 is a high performance, low power; full-featured single-chip stereo FM receiver designed for mini-speakers,
MP3 players. It integrates FM receive functions, auto-seek and clear channel scan. Advanced digital architecture enables
superior receiver sensitivity and crystal clear audio.
With its small footprint, minimal external component count and multiple crystal clock frequency support, the QN8075 is
easy to integrate into a variety of small form-factor low power portable applications.
_______________________________ Key Features ___________________________
• Worldwide FM Band Coverage
• 60 MHz to 108 MHz full band tuning in
50/100/200 kHz step sizes
• 50/75μs de-emphasis
• Ease of Integration
• Small footprint, available in SOP16 and SSOP16
package
• 32.768 kHz and Multiple MHz crystal and direct
clock input supported
• I2C control interface
• Very Low Power Consumption
• 12.8mA typical
• VCC: 2.7~5.0V, integrated LDO, support battery
direct connection
• Power saving Standby mode
• Low shutdown leakage current
• Accommodate 1.6~3.6V digital interface
• Direct Earphone Driving
• Adaptive Noise Cancellation
• Integrated adaptive noise cancellation (SNC, HCC,
SM)
• Volume Control
• High Performance
• Superior sensitivity, 1.4 µVEMF
• 65dB stereo SNR, 0.03% THD
• Improved auto channel seek and fast tune
• L/R separation 44dB
• Robust Operation
• -250C to +850C operation
• ESD protection on all input and output pads
• 1 KHz Tone Generator Inside
___________________________ Typical Applications ________________________
• Portable Audio & Media Players
• Portable radios
• Mini-speakers
QN8075 Functional Blocks:
Rev 0.2c (09/02)
Copyright ©2011 by Quintic Corporation
Page 1
Confidential A
Confidential Information contained herein is covered under Non-Disclosure Agreement (NDA).
Advance Technical Information. This is a product under development. Characteristics and specifications are subject to change without notice.
Free Datasheet http://www.Datasheet4U.com
Table 6: Receiver Characteristics
(Typical values are at Vcc = 3.3V, f carrier=88 MHz and TA = 25oC).
SYMBOL
SRX
IP3
RejAM
Rin
SRX_Adj
SRX_Alt
PARAMETERS
FM sensitivity
Input referred IP3
AM suppression
RF input impedance
Adjacent channel
rejection
Alternate channel
rejection
SNRaudio_in Audio SNR
THDaudio_in Audio THD
αLR in
AttPilot
BLR
L/R separation
Pilot rejection
L/R channel imbalance
τemph1
De-emphasis time
constant
Vaudio out
RLOAD
CLOAD
RSSIerr
THDdriver
Audio output voltage
Audio output Loading
Resistance
Audio output loading
capacitance
RSSI uncertainty
Audio THD after
earphone driver
Notes:
1. Guaranteed by design.
CONDITIONS
(S+N)/N = 26dB
At maximum gain
At pin RFI
200 kHz offset
400 kHz offset
MONO, Δf = 22.5 kHz1
STEREO, Δf = 67.5 kHz, Δfpilot =
6.75 kHz
MONO, Δf = 75 kHz
STEREO, Δf = 67.5 kHz, Δfpilot =
6.75 kHz
L and R channel gain imbalance
at 1 kHz offset from DC
PETC = 1
PETC = 0
Peak-Peak, single ended
RLOAD=32Ω, 1 Vpp output
RLOAD=1kΩ, 1 Vpp output
MIN
71.3
47.5
32
-3
TYP
1.4
120
52
5
49
MAX
UNIT
μVEMF
dBμV
dB
kΩ
dB
62
58
67
0.04
0.03
47
70
1
75 78.7
50 52.5
11
dB
dB
%
%
dB
dB
dB
μs
μs
V
Ω
20 pF
3 dB
0.05
%
0.03
Table 7: Timing Characteristics
(Typical values are at Vcc = 3.3V and TA = 25oC).
Rev 0.2c (09/02)
Copyright ©2011 by Quintic Corporation
Page 6
Confidential A
Confidential Information contained herein is covered under Non-Disclosure Agreement (NDA).
Advance Technical Information. This is a product under development. Characteristics and specifications are subject to change without notice.
Free Datasheet http://www.Datasheet4U.com
6 Page 4 Control Interface Protocol
The QN8075 supports the standard I2C serial interfaces.
At power-on, all register bits are set to default values.
I2C Serial Control Interface
QN8075 provides an I2C-compatible serial interface. It
consists of two wires; serial bi-directional data line
(SDA) and input clock line (SCL). It operates as a slave
on the bus and the slave address is 0010000. The data
transfer rate on the bus is up to 400 Kbit/s.
SDA must be stable during the high period of SCL,
except for start and stop conditions. SDA can only
change with SCL being low. A high-to-low transition on
SDA while SCL is high indicates a start condition. A
low-to-high transition on SDA while SCL is high
indicates a stop condition.
An I2C master initiates a data transfer by generating a
start condition followed by the QN8075 slave address,
MSB first, followed by a 0 to indicate a write cycle.
After receiving an ACK from the QN8075 (by pulling
SDA low), the master sends the sub-address of the
register, or the first of a block of registers it wants to
write, followed by one or more bytes of data, MSB first.
The QN8075 acknowledges each byte after completion
of each transfer. The I2C master terminates the write
operation by generating a stop condition (P).
The read operation consists of two phases. The first
phase is the address phase. In this phase, an I2C master
initiates a write operation to the QN8075 by generating a
start condition (S) followed by the QN8075 slave address,
MSB first, followed by a 0 to indicate a write cycle.
After receiving ACK from the QN8075, the master sends
the sub-address of the register or the first of a block of
registers it wants to read. After the cycle is
acknowledged, the master terminates the cycle
immediately by generating a stop condition (P).
The second phase is the data phase. In this phase, an I2C
master initiates a read operation to the QN8075 by
generating a start condition followed by the QN8075
slave address, MSB first, followed by a 1 to indicate a
read cycle. After an acknowledge from the QN8075, the
I2C master receives one or more bytes of data from the
QN8075. The I2C master acknowledges the transfer at the
end of each byte. After the last data byte to be sent has
been transferred from the QN8075 to the master, the
master generates a NACK followed by a stop.
The timing diagrams below illustrate both write and read operations.
Notes:
1.
2.
Figure 6 I2C Serial Control Interface Protocol
The default IC address is 0010000.
“20” for a WRITE operation, “21” for a READ operation.
Rev 0.2c (09/02)
Copyright ©2011 by Quintic Corporation
Page 12
Confidential A
Confidential Information contained herein is covered under Non-Disclosure Agreement (NDA).
Advance Technical Information. This is a product under development. Characteristics and specifications are subject to change without notice.
Free Datasheet http://www.Datasheet4U.com
12 Page | ||
Seiten | Gesamt 19 Seiten | |
PDF Download | [ QN8075 Schematic.PDF ] |
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