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AN6-206 Schematic ( PDF Datasheet ) - Fairchild Semiconductor

Teilenummer AN6-206
Beschreibung Primary-Side Synchronous Rectifier (SR) Trigger Solution
Hersteller Fairchild Semiconductor
Logo Fairchild Semiconductor Logo 




Gesamt 9 Seiten
AN6-206 Datasheet, Funktion
www.fairchildsemi.com
AN-6206
Primary-Side Synchronous Rectifier (SR) Trigger Solution
for Dual-Forward Converter
Introduction
In any switching converter, rectifier diodes are used to
obtain DC output voltage. The conduction loss of diode
rectifier contributes significantly to the overall power losses
in a power supply; especially in low output voltage
applications, such as personal computer (PC) power
supplies. The conduction loss of a rectifier is proportional to
the product of its forward-voltage drop and the forward
conduction current. Using synchronous rectification (SR)
where the rectifier diode is replaced by MOSFET with
proper on resistance (RdsON), the forward-voltage drop of a
synchronous rectifier can be lower than that of a diode
rectifier and, consequently, the rectifier conduction loss can
be reduced.
The highly integrated FAN6210 is a primary-side SR
controller for dual-forward converter that provides control
signals for the secondary-side SR driver FAN6206.
FAN6210 also provides drive signal for the primary-side
power switches by using an output signal from the PWM
controller. FAN6210 can be combined with any PWM
controller that can drive a dual-forward converter. To obtain
optimal timing for the SR drive signals, transformer winding
voltage is also monitored. To improve light-load efficiency,
green-mode operation is employed, which disables the SR
turn-on trigger signal, minimizing gate drive power
consumption at light-load condition.
This application note describes the design procedure of SR
circuit using FAN6210 and FAN6206. The guidelines for
printed circuit board (PCB) layout and a design example
with experiment results are also presented.
Vin
Vac PFC stage
Cbulk
Drv n:1
R8
D1
PWM control signal
(From PWM controller)
R1
FAN6210
1 XP GND 8
2 XN SOUT 7
3 SIN VDD 6
4 RDLY DET 5
C1
D5 D3 R3
D6 D4 R4
R2
Drv
D2
From power supply
of PWM controller
R5
PT
Q1 R9
R6 R7
FAN6206
1 LPC1GATE1 8
2 LPC2 GND 7
3 SN GATE2 6
4 SP VDD 5
Figure 1. Typical Application
Lo
Q2
C2
Vo
© 2010 Fairchild Semiconductor Corporation
Rev. 1.0.0 • 4/27/10
www.fairchildsemi.com
Free Datasheet http://www.Datasheet4U.com






AN6-206 Datasheet, Funktion
AN-6206
APPLICATION NOTE
Design Example
The following example is a 12V/300W PC power supply, in
which the dual-forward topology is used. As Figure 13
shows, the FAN4801 integrated CCM PFC/PWM
combination controller is used as the controller for both PFC
stage and PWM stage.
The basic system parameters are listed in Table 1.The two-
level Vbulk is derived from FAN4801. The typical voltage
level for Vbulk is 380V; but under low-line and light-load
condition, Vbulk is 310V for decreasing power loss at the
PFC stage. The typical switching frequency (fs) is 65kHz for
both PFC and PWM stage.
In a typical PC power application, multi-output is necessary.
If the 12V output terminal is used to generate other output
terminals, SG6520 can be the proper supervisor IC. The
power supply of the supervisor is from 5V standby output
terminal. Flyback topology is the general structure for
standby power. The following measurements include
standby loading. FAN6751 is chosen to be the PWM
controller of standby stage.
From the specification, all critical components are treated
and final measurement results are given. Base on the design
guideline, the critical parameters are calculated and
summarized in Table 2.
Table 1. System Specification
Input
Input Voltage Range
Line Frequency Range
Output Voltage of PFC Stage (Vbulk)
90~264VAC
47~63Hz
310V / 380V
Output
Output Voltage (Vo)
Output Power (Po)
Typical Switching Frequency (fs)
12V
300W
65kHz
In addition to low-line and light-load condition, Vbulk is
boosted to 380V. The turn ratio n for of TX1 is 11, hence the
Vds voltage during PWM turn-on period is 380/11=34.55V.
According to Equation 4, RatioLPC2 = 1/11.5. The divided
voltage on LPC2 is 3.00V. According to Equation 3, the
plateau divided voltage on LPC1 during PWM turn-off
period should be between 3V~5V. Select RatioLPC2 = 1/7.8,
then the divided voltage is 4.43V. Select R9 = 10kand R8
= 105k, then R7 = 10kand R6 = 68k. Under low-line
and light-load condition, Vbulk is decreased to 310V. The
divided voltage on LPC2 is 2.45V, while the divided voltage
on LPC1 is 3.61V.
PFC stage
(controlled by FAN4801)
+
-
=12V
IPWM
(To FAN4801)
OPWM
(From FAN4801)
1 XP GND 8
2 XN SOUT 7
3 SIN VDD 6
4 RDLY DET 5
From VDD
of FAN4801
1 LPC1GATE1 8
2 LPC2 GND 7
3 SN GATE2 6
4 SP VDD 5
Supervisor
Power supply is from
5V standby output
© 2010 Fairchild Semiconductor Corporation
Rev. 1.0.0 • 4/27/10
Figure 13.Complete Circuit Diagram
6
www.fairchildsemi.com
Free Datasheet http://www.Datasheet4U.com

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