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PDF RTD2545L Data sheet ( Hoja de datos )

Número de pieza RTD2545L
Descripción Flat Panel Display Controller
Fabricantes Realtek 
Logotipo Realtek Logotipo



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No Preview Available ! RTD2545L Hoja de datos, Descripción, Manual

Realtek
RTD2545L Series
RTD2545L Series
Flat Panel Display Controller
Fully Technology
Version 1.01
Last updated: 2007/9/28
Free Datasheet http://www.0PDF.com

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RTD2545L pdf
Realtek
RTD2545L Series
2. Features
General
l Programmable Scaling up and down
l No external memory required.
l Require only one crystal to generate all timing.
l Programmable 3.3V detection for multi-power
domain in a system
l 2 channels 8 bits PWM output, and wide range
selectable PWM frequency.
l Support input format up to 1920/1440
width(optional)
l DDC/CI(MCCS) supported
Analog RGB Input Interface
l Integrated 8-bit triple-channel 210/165 MHz
ADC/PLL (optional)
l Embedded programmable Schmitt trigger of
HSYNC
l Support Sync On Green (SOG) and various kinds
of composite sync modes
l On-chip high-performance hybrid PLLs
l High resolution true 64 phase ADC PLL
l Auto Black Level Adjustment
Digital Video Input Interface (Optional)
l Support 8-bit video (ITU 656) format input
l Built-in YUV to RGB color space converter &
de-interlace
DVI Compliant Digital Input Interface
(Optional)
l Single link on-chip TMDS receiver
l Up to 165Mhz
l Adaptive algorithm for TMDS capability
l Data enable only mode support
l HDCP 1.1 supported (optional)
Auto Detection /Auto Calibration
l Input format detection
l Compatibility with standard VESA mode and
support user-defined mode
l Smart engine for Phase/Image position/Color
calibration
Scaling
l Fully programmable zoom ratios
l Independent horizontal/vertical scaling
l Advanced zoom algorithm provides high image
quality
l Sharpness/Smooth filter enhancement
l Support non-linear scaling from 4:3 to 16:9 or
16:9 to 4:3
Vivid Color™
l True 10 bits color processing engine
l Dynamic Contrast Control engine(DCC) (Patent
Pending)
l Independent Color Management (ICM)
l sRGB compliance
l Advanced Dithering logic for 18-bit panel color
depth enhancement
l Peaking and Coring function supported
l Dynamic overshoot-smear canceling engine
l Brightness and contrast control
l Programmable 10-bit gamma support
Output Interface
l Fully programmable display timing generator
l 1 and 2 pixel/clock panel support and up to
170MHz, 1920/1440-pixel width (optional)
l Support LVDS output interface
l Spread-Spectrum DPLL to reduce EMI
l Fixed Last Line output for perfect panel
capability
Host Interface
l Support MCU serial bus interface.
l Support MCU dual edge data latch.
Embedded OSD
l Embedded 16.5K SRAM dynamically stores
OSD command and fonts
l Support multi-color RAM font, 1, 2 and 4-bit per
pixel
l 16 color palette with 24bit true color selection
l Maximum 8 window with alpha-blending/
gradient/dynamic fade-in/fade-out, bordering/
shadow/3D window type
l Rotary 90,180,270 degree
l Independent row shadowing/bordering
l Programmable blinking effects for each character
l OSD-made internal pattern generator for factory
mode
l Support 12x18~4x18 hardware proportional font
l Decompress OSD font
Power & Technology
l 3.3V power supplier
l 0.18um CMOS process,48 pin QFN package
l Embedded 3.3V to 1.8V voltage regulator
5
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RTD2545L arduino
Realtek
RTD2545L Series
5. Functional Description
5.1 Input
Digital Input (ITU 656)
RTD is designed to connect the interface of digital signal from video decoder. Input data is latched
within a capture window defined in registers. The timing scheme designed for input devices are
showed in the following diagram.
There are not H syncV sync signals provided by the video decoder with ITU BT.656, these
synchronal signals have to be generated by decoding the EAV & SAV timing reference signals.
VGBCLK
VGB_R(Byte)
xxx
U0 Y0 V0 Y1 U2
Figure 3 Input YUV 4:2:2(8-bits) Timing
Only 254 of possible 256 8-bit words may be used to express a signal value, 0 and 255 are reserved
for data identification purposes. Video 8 data stream is as below:
Blanking Timing reference 720 pixels YUV 422 DATA
Timing reference Blanking
period
code
code period
80 10 FF 00 00 SAV Cb0 Y0 Cr0 Y1 Cb2 Y2 Cr718 Y719 FF 00 00 EAV 80 10
Cbn: U(B-Y) colour difference component
Yn : luminance component
Crn: V(R-Y) colour difference component
SAV/EAV format
Bit 7 Bit 6(F)
1 Field bit
1st field F=0
2nd field F=1
Bit 5(V)
Bit 4(H) Bit
Bit
3(P3) 2(P2)
Vertical blanking bit V=1 H=0 in SAV Protection bits
Active video V=0
H=1 in EAV
Bit
1(P1)
Bit
0(P0)
11
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