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AW6688 Schematic ( PDF Datasheet ) - AWINIC

Teilenummer AW6688
Beschreibung Stand-Alone Ethernet Controller
Hersteller AWINIC
Logo AWINIC Logo 




Gesamt 24 Seiten
AW6688 Datasheet, Funktion
AW6688 Datasheet
December 2011 V1.0
Stand-Alone Ethernet Controller
FEATURES
5X5 mm, 32-pin QFN
Compatible with Motorola SPI SPEC
Input clock frequency up to 60MHz
Only support phase 0
Only support polarity 0
IEEE 802.3 compatible Ethernet controller
Fully compatible with 10/100 BASE-T
networks
Integrated MAC and 10/100 PHY
Supports full and half duplex modes
Programmable padding and CRC
generation
Programmable padding and CRC stripping
Programmable flow control
Supports Ethernet frame length up to
1522 bytes
Flexible address filtering modes
8k byte receive buffer
4k byte transmit buffer
Multi-function LED output
2.8V IO supply and 1.2V core supply
CMOS process technology
The AW6688 adopts TRQ5x5-32L package:
INTR 25
GND_D 26
VCC12D 27
NC 28
NC 29
TE 30
NC 31
GND_D 32
AW6688
33
GND_A
16 CKO
15 LED1
14 LED0
13 RSTN
12 NC
11 NC
10 NC
9 GND_A
Copyright© 2008 by AWINIC Technology Co. Ltd.
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AW6688 Datasheet, Funktion
AW6688 Datasheet
December 2011 V1.0
Name
Number Type Dir
NC 31
GND_D 32
GND
GND_A 33
GND
Note:
PWR: power
GND: ground
ANA: analog function pin
PU: pull up digital function pin
PD: pull down digital function pin
XTAL: crystal pin
Description
Digital ground
Analog ground, located at the centre of the bottom
Copyright© 2008 by AWINIC Technology Co. Ltd.
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AW6688 pdf, datenblatt
AW6688 Datasheet
December 2011 V1.0
in the SPI command. The difference between this command and the write INT REG command is
that the registers of the MAC written by the command will not cross the word (32 bit) boundary.
For example if the address in the SPI command is point to 0x001, then only the first three data
bytes will be written to address 0x001, 0x002 and 0x003. All the data bytes following will be
dropped by the SPI interface. So the maximum number of the valid data byte is 4 in this SPI
command.
Figure 5 SPI write MAC register timing
CSN
SCK
MOSI
MSB
LSB MSB
LSB MSB
LSB MSB
LSB
MISO
B0 B1 B2
SPI command ID
and parameter
SPI command
parameter
SPI payload 0
SPI payload
Byte N
SPI payload
N-2
6.1.4 Read MAC REG Command
The command ID of the write MAC REG command is 4’b0011. This command is used to read the
MAC control registers. The address in the command is the byte address of the first data byte in
the SPI command. The difference between this command and the read INT REG command is
that the registers of the MAC read by the command will not cross the word (32 bit) boundary. For
example if the address in the SPI command is point to 0x001, then only the first three data bytes
will be valid and is read from the address 0x001, 0x002 and 0x003. All the data bytes following
shall be dropped by the SPI master. So the maximum number of the valid data byte is 4 in this
SPI command.
Figure 6 SPI read MAC register timing
Copyright© 2008 by AWINIC Technology Co. Ltd.
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