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K4B1G1646G Schematic ( PDF Datasheet ) - Samsung

Teilenummer K4B1G1646G
Beschreibung 1Gb G-die DDR3 SDRAM
Hersteller Samsung
Logo Samsung Logo 




Gesamt 30 Seiten
K4B1G1646G Datasheet, Funktion
Rev. 1.11, Jun. 2011
K4B1G1646G
1Gb G-die DDR3 SDRAM x16 only
96FBGA with Lead-Free & Halogen-Free
(RoHS compliant)
datasheet
SAMSUNG ELECTRONICS RESERVES THE RIGHT TO CHANGE PRODUCTS, INFORMATION AND
SPECIFICATIONS WITHOUT NOTICE.
Products and specifications discussed herein are for reference purposes only. All information discussed
herein is provided on an "AS IS" basis, without warranties of any kind.
This document and all information discussed herein remain the sole and exclusive property of Samsung
Electronics. No license of any patent, copyright, mask work, trademark or any other intellectual property
right is granted by one party to the other party under this document, by implication, estoppel or other-
wise.
Samsung products are not intended for use in life support, critical care, medical, safety equipment, or
similar applications where product failure could result in loss of life or personal or physical harm, or any
military or defense application, or any governmental procurement to which special terms or provisions
may apply.
For updates or additional information about Samsung products, contact your nearest Samsung office.
All brand names, trademarks and registered trademarks belong to their respective owners.
2011 Samsung Electronics Co., Ltd. All rights reserved.
-1-
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K4B1G1646G Datasheet, Funktion
K4B1G1646G
datasheet
3. Package pinout/Mechanical Dimension & Addressing
3.1 x16 Package Pinout (Top view) : 96ball FBGA Package
Rev. 1.11
DDR3 SDRAM
1
2
3 456 7
8
A
VDDQ
DQU5
DQU7
B VSSQ VDD
VSS
C
VDDQ
DQU3
DQU1
D
VSSQ
VDDQ
DMU
E
VSS
VSSQ
DQL0
F
VDDQ
DQL2
DQSL
G
VSSQ
DQL6
DQSL
H
VREFDQ
VDDQ
DQL4
J NC VSS RAS
K ODT VDD CAS
L NC CS WE
M VSS BA0 BA2
N VDD
A3
A0
P VSS
A5
A2
R VDD
A7
A9
T VSS RESET NC
DQU4
DQSU
DQSU
DQU0
DML
DQL1
VDD
DQL7
CK
CK
A10/AP
NC
A12/BC
A1
A11
NC
VDDQ
DQU6
DQU2
VSSQ
VSSQ
DQL3
VSS
DQL5
VSS
VDD
ZQ
VREFCA
BA1
A4
A6
A8
9
VSS
VSSQ
VDDQ
VDD
VDDQ
VSSQ
VSSQ
VDDQ
NC
CKE
NC
VSS
VDD
VSS
VDD
VSS
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
T
Ball Locations (x16)
Populated ball
Ball not populated
Top view
(See the balls through the package)
123456789
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
T
-6-
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K4B1G1646G pdf, datenblatt
K4B1G1646G
datasheet
Rev. 1.11
DDR3 SDRAM
8.2 VREF Tolerances
The dc-tolerance limits and ac-noise limits for the reference voltages VREFCA and VREFDQ are illustrate in Figure 1. It shows a valid reference voltage
VREF(t) as a function of time. (VREF stands for VREFCA and VREFDQ likewise).
VREF(DC) is the linear average of VREF(t) over a very long period of time (e.g. 1 sec). This average has to meet the min/max requirement in Table 7 on
page 11. Furthermore VREF(t) may temporarily deviate from VREF(DC) by no more than ± 1% VDD.
voltage
VDD
VSS
time
Figure 1. Illustration of VREF(DC) tolerance and VREF ac-noise limits
The voltage levels for setup and hold time measurements VIH(AC), VIH(DC), VIL(AC) and VIL(DC) are dependent on VREF.
"VREF" shall be understood as VREF(DC), as defined in Figure 1 .
This clarifies, that dc-variations of VREF affect the absolute voltage a signal has to reach to achieve a valid high or low level and therefore the time to
which setup and hold is measured. System timing and voltage budgets need to account for VREF(DC) deviations from the optimum position within the
data-eye of the input signals.
This also clarifies that the DRAM setup/hold specification and derating values need to include time and voltage associated with VREF ac-noise. Timing
and voltage effects due to ac-noise on VREF up to the specified limit (+/-1% of VDD) are included in DRAM timings and their associated deratings.
- 12 -
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