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PA1418 Schematic ( PDF Datasheet ) - Protek Devices

Teilenummer PA1418
Beschreibung Radio Transmitter
Hersteller Protek Devices
Logo Protek Devices Logo 




Gesamt 19 Seiten
PA1418 Datasheet, Funktion
ANALOG PRODUCT DIVISION
PA1418 Technical Note
Introduction
This is a reference note for Protek Analog’s PA1418. The document includes data for the IC, recommended
external components, and other pertinent information.
Please read all instructions and recommendations before beginning to design any product that is to include this
device. This document contains a checklist to reference before powering up completed circuit and
troubleshooting procedures outlining causes and countermeasures for issues arising in the application of the IC.
Contact information is included if this document is insufficient to answer any problems or questions that may
arise.
Contents
1. Overview.
1.1. Features
1.2. Block Diagrams
24TSSOP Pin out
32 QFN Pin out
1.3. Absolute Maximum Ratings
1.4. Operating Range
2. Operation.
3. Navigator.
4. Explanation of External Parts.
4.1. Pre-Emphasis
4.2. Limiter
4.3. Low-Pass Filter
4.4. Half VDD Filter
4.5. Composite Signal Adjust
4.6. RF Oscillator
4.7. RF Output
4.8. X’TAL Oscillator
4.9. Serial Data Input
4.10. Phase Lock Loop
4.11. Audio Mute
4.12. Pilot Signal Adjust
5. PCB Sample and Recommendations.
1. Overview:
The PA1418 is a Radio Transmitter that can send audio signals from personal computers, game consoles or
independent devices to any type of audio equipment with a built in FM receiver.
The IC consists of a Pre-Emphasis circuit that improves Signal to Noise Ratio (S/N), a Limiter circuit that
prevents over-modulation and a low Pass filter (LPF) circuit that limits the maximum modulation frequency. The
Stereo modulation circuit generates stereo composite signals through a FM transmitter circuit with Phase-
Locked Loop (PLL) frequency synthesizers.
1. 1. Features
1. Improved Audio Quality due to integrated Pre-emphasis, limiter and Low-pass filter circuits.
2. Pilot tone FM stereo modulation circuit is integrated.
3. An incorporated PLL frequency synthesizer ensures a stable FM transmission frequency.
4. Device utilizes a serial data control method to set the frequency via a microcontroller.
5. Integrated mute option.
561 E Elliot Road. Chandler, AZ 85225 Tel: (480) 539-2900. Fax: (480) 632-1715.
www.protekanalog.com
Free Datasheet http://www.nDatasheet.com






PA1418 Datasheet, Funktion
ANALOG PRODUCT DIVISION
PA1418 Technical Note
2. Operation: (Pin numbers reference 24 TSSOP package)
The PA1418, FM stereo transmitter IC made by ProTek
Analog includes all the processing circuitry required for
stereo FM transmission and also the crystal control
section, which provides precise frequency locking
As shown, the PA1418 includes two separate audio
processing sections, for the left and right channels. The
left-channel audio signal is applied to pin 24 of the chip,
while the right channel signal is applied to pin 1. These
audio signals are then applied to a pre-emphasis circuit,
which boosts those frequencies above a 50ms time
constant (i.e., those frequencies above 3.183 kHz) prior
to transmission
Pre-emphasis is used to improve the signal-to-noise ratio
of the received FM signal. It works by using a
complementary de-emphasis circuit in the receiver to
attenuate the boosted treble frequencies after
demodulation, restoring the frequency response is
restored to normal. At the same time, this also
significantly reduces the ‘hiss” sound that would
otherwise be evident in the signal
The amount of pre-emphasis is set by the value of the
capacitors connected to pins 2 & 23, (Signal limiting is
also provided within the pre-emphasis section). This
involves attenuating signals above a certain threshold
to prevent overloading succeeding stages also
preventing over-modulation and reduces distortion. The
pre-emphasized signals for the left and right channels
are then processed through two low-pass filter (LPF)
stages, designed at15kHz. This roll-off is necessary to
restrict the bandwidth of the FM signal and is the same
frequency limit used by commercial broadcast FM
transmitters.
In addition, the 1.9MHz signal is divided by 76 to give a
100 kHz signal. This signal is then applied to the phase
detector, which also monitors the program counter
output. This program counter is actually a
programmable dual modulus divider, which outputs a
divided down value of the RF signal.
The division ratio is set by programming the counter
with a 6 and 5 bit number. More information on the
working of the dual modulus divider is given in section I
of “Explanation of External Parts”
The phase detector output produces an error signal to
control the voltage applied to a varicap diode and forms
part of the RF oscillator at pin 10. Its frequency of
oscillation is determined by the value of the inductance
and the total parallel capacitance.
Since the varicap diode forms part of this capacitance,
we can alter the RF oscillator frequency by varying its
value. In operation, the varicap diode's capacitance
varies in proportion to the DC voltage applied to it by
the output of the PLL phase detector. The phase
detector adjusts the varicap voltage so that the divided
RF oscillator frequency is 100 kHz at the program
counter output. If the RF frequency drifts high, the
frequency output from the programmable divider rises
and the phase detector will "see" an error between this
and the 100 kHz signal. As a result, the phase detector
reduces the DC voltage applied to the varicap diode,
thereby increasing its capacitance. And this in turn
decreases the oscillator frequency to bring it back into
"lock".
The outputs from the left and right LPF channels are in
turn applied to a multiplex (MPX) block. This is used to
effectively produce sum (left + right) and difference (left
- right) signals which are then modulated onto a 38 kHz
carrier. The carrier is then suppressed (or removed) to
provide a double-sideband suppressed carrier
(DSBSC) signal. It is then mixed in a summing (+) block
with a 19 kHz pilot tone to give a composite signal
output (with full stereo encoding) at pin 5.
The phase and level of the 19 kHz pilot tone are set
using a resistor and a capacitor at pin 21.The 38 kHz
multiplex signal and 19 kHz pilot tone are derived by
dividing down the 7.6MHz crystal oscillator located at
pins 14 & 15. The 7.6MHz crystal frequency is divided
by 25 to provide a 304 kHz signal. This 304 kHz signal
is used by the audio multiplexer and an 8-bit DAC to
generate the composite signal with the subcarriers (38
kHz). The 76MHz frequency is also divided by 50 to
generate a 152 kHz frequency. This signal is used by
the pilot signal into the composite audio.
Conversely, if the RF frequency drifts low, the
programmable divider output will be lower than 100
kHz. This means that the phase detector now increases
the applied DC voltage to the varicap to decrease its
capacitance and raise the RF frequency. As a result,
this PLL feedback arrangement ensures that the
programmable divider output remains fixed at 100 kHz
and thus ensures stability of the RF oscillator.
By changing the programmable divider we can change
the RF frequency. So, for example, if we set the divider
to 1079, the RF oscillator must operate at 107.9MHz for
the programmable divider output to remain at 100 kHz.
The RF frequency is modulated by the voltage applied
to the varicap diode using the composite signal output
at pin 5.The average frequency of the RF oscillator
remains fixed, as set by the programmable divider. As
a result, the transmitted FM signal varies either side of
the carrier frequency according to the composite signal
level - i.e., it is frequency modulated.
561 E Elliot Road. Chandler, AZ 85225 Tel: (480) 539-2900. Fax: (480) 632-1715.
www.protekanalog.com
Free Datasheet http://www.nDatasheet.com

6 Page









PA1418 pdf, datenblatt
ANALOG PRODUCT DIVISION
PA1418 Technical Note
4.8. X’TAL Oscillator (Pin 14, 15)
A 7.60 MHz crystal oscillator is needed between pins 14 and 15 coupled with its 27pF load capacitors (C1 and
C2) as shown the the folowing drawing.
15
Rf
14
13
C1
7.60MHz
C2
The crystal needs to be placed as near as possible to the device output pins to minimize stray capacitance.
Please no not run any wires or traces near or under the oscillator as it is very suseptable to interference. If
possible, place a ground plane directly under the crystal to further insulate it from any nearby signals.
4.9. Serial Data Input (Pin 17, 18, 19)
The VIH level for the inpt voltage at the serial data input is 0.8Vcc to Vcc and the VIL level is GND to 0.2Vcc.
Please note that the operating voltage of the microcontroller can be different from the operating voltage of the IC.
It is also important to keep in mind that there needs to be a small delay betweeen powering on the IC and
inputing the serial data. The initial logic is set as “unfixed” upon startup and some circuits such as the PLL will
not function correctly instantaniously.
Phase
Detector
Mono/Stereo
1
2
11
19
18
Dual
Modulus
Divider
17
6
PA1418 – Serial Programming Interface:
The PA1418 has a 3-pin serial programming port. This port consists of pins CE (Chip Enable), CK (Clock) and
DA (Data). The timing sequence of these signals is as shown in figure 1. Using these ports a 16-bit word can be
fed into the chip to form various division ratios as well as other control bits.
561 E Elliot Road. Chandler, AZ 85225 Tel: (480) 539-2900. Fax: (480) 632-1715.
www.protekanalog.com
Free Datasheet http://www.nDatasheet.com

12 Page





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