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95V857 Schematic ( PDF Datasheet ) - Integrated Circuit Systems

Teilenummer 95V857
Beschreibung ICS95V857
Hersteller Integrated Circuit Systems
Logo Integrated Circuit Systems Logo 




Gesamt 13 Seiten
95V857 Datasheet, Funktion
Integrated
Circuit
Systems, Inc.
ICS95V8 5 7
2.5V Wide Range Frequency Clock Driver (45MHz - 233MHz)
Recommended Application:
• DDR Memory Modules / Zero Delay Board Fan Out
• Provides complete DDR registered DIMM solution
with ICSSSTVF16857, ICSSSTVF16859 or
ICSSSTV32852
Product Description/Features:
• Low skew, low jitter PLL clock driver
• 1 to 10 differential clock distribution (SSTL_2)
• Feedback pins for input to output synchronization
• PD# for power management
• Spread Spectrum-tolerant inputs
• Auto PD when input signal removed
Specifications:
• Meets PC3200 Class A+ specification for DDR-I 400
support
• Covers all DDRI speed grades
Switching Characteristics:
• CYCLE - CYCLE jitter: <50ps
• OUTPUT - OUTPUT skew: <40ps
• Period jitter: ±30ps
Pin Configuration
GND
CLKC0
CLKT0
VDD
CLKT1
CLKC1
GND
GND
CLKC2
CLKT2
VDD
VDD
CLK_INT
CLK_INC
VDD
AVDD
AGND
GND
CLKC3
CLKT3
VDD
CLKT4
CLKC4
GND
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
48 GND
47 CLKC5
46 CLKT5
45 VDD
44 CLKT6
43 CLKC6
42 GND
41 GND
40 CLKC7
39 CLKT7
38 VDD
37 PD#
36 FB_INT
35 FB_INC
34 VDD
33 FB_OUTC
32 FB_OUTT
31 GND
30 CLKC8
29 CLKT8
28 VDD
27 CLKT9
26 CLKC9
25 GND
48-Pin TSSOP/TVSOP
6.10 mm Body, 0.50 mm Pitch = TSSOP
4.40 mm Body, 0.40 mm Pitch = TVSOP
Block Diagram
Functionality
INPUTS
OUTPUTS
PLL State
AVDD PD# CLK_INT CLK_INC CLKT CLKC FB_OUTT FB_OUTC
GND H
L
H LH L
H Bypassed/off
GND
2.5V
(nom)
2.5V
(nom)
2.5V
(nom)
2.5V
(nom)
2.5V
(nom)
H
L
L
H
H
X
HL
LH
HL
LH
HL
<20MHz)(1)
HL
ZZ
ZZ
LH
HL
ZZ
H
Z
Z
L
H
Z
L Bypassed/off
Z off
Z off
H on
L on
Z off
PD#
FB_INT
FB_INC
CLK_INC
CLK_INT
Control
Logic
PLL
0674U01/27/09
FB_OUTT
FB_OUTC
CLKT0
CLKC0
CLKT1
CLKC1
CLKT2
CLKC2
CLKT3
CLKC3
CLKT4
CLKC4
CLKT5
CLKC5
CLKT6
CLKC6
CLKT7
CLKC7
CLKT8
CLKC8
CLKT9
CLKC9
Free Datasheet http://www.nDatasheet.com






95V857 Datasheet, Funktion
ICS95V8 5 7
Timing Requirements
TA = 0 - 85°C; Supply Voltage AVDD, VDD = 2.5 V +/- 0.2V (unless otherwise stated)
PARAMETER
SYMBOL
CONDITIONS
MIN MAX
Max clock frequency
freqop
2.5V+0.2V @ 25oC
45 233
Application Frequency
Range
freqApp
2.5V+0.2V @ 25oC
95 220
Input clock duty cycle
dtin
40 60
UNITS
MHz
MHz
%
CLK stabilization
TSTAB
15 µs
Switching Characteristics (see note 3)
PARAMETER
SYMBOL
CONDITION
MIN TYP
Low-to high level
propagation delay time
tPLH1
CLK_IN to any output
3.5
High-to low level propagation
delay time
tPLL1
CLK_IN to any output
3.5
Output enable time
Output disable time
tEN PD# to any output
tdis PD# to any output
3
3
Period jitter
Half-period jitter
Tjit (per)
t(jit_hper)
100MHz to 200MHz
100MHz to 200MHz
-30
-75
Input clock slew rate
tsl(i)
1
Output clock slew rate
tsl(o)
1
Cycle to Cycle Jitter1
Tcyc-Tcyc 100MHz to 200MHz
-50
Static Phase Offset
t(static
phase
4
offset)
-50
Output to Output Skew
Tskew
Notes:
1. Refers to transition on noninverting output in PLL bypass mode.
2. While the pulse skew is almost constant over frequency, the duty cycle error
increases at higher frequencies.This is due to the formula: duty cycle=twH/tc, where
the cycle (tc) decreases as the frequency goes up.
3. Switching characteristics guaranteed for application frequency range.
4. Static phase offset shifted by design.
0
MAX UNITS
ns
ns
ns
ns
30 ps
75 ps
4 V/ns
2 V/ns
50 ps
50 ps
40 ps
0674U01/27/09
6
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6 Page









95V857 pdf, datenblatt
ICS95V8 5 7
Index Area
N
1
2
E
Top View
D
Seating Plane
A1
Anvil
Singulation
or
Sawn
Singulation
A
0.08 C
A3 L
(ND-1)x e
(Ref.)
N
E2 E2
2
e
(Ref.)
ND & NE
Odd
C
D2
2
D2
(Ref.)
ND & NE
Even
e (Typ.)
2 If ND & NE
1 are Even
2
(NE -1)x e
(Ref.)
b
Thermal
Base
THERMALLY ENHANCED, VERY THIN, FINE PITCH
QUAD FLAT / NO LEAD PLASTIC PACKAGE
ALL DIMENSIONS IN MILLIMETERS
N
40
SYMBOL
MIN.
MAX.
ND
NE
D x E BASIC
D2 MIN. / MAX.
10
10
6.00 x 6.00
2.75 / 3.05
A
A1
A3
b
0.80
1.00
0 0.05
0.25 Reference
0.18
0.30
E2 MIN. / MAX. 2.75 / 3.05
e
0.50 BASIC
L MIN. / MAX.
0.30 / 0.50
Source Reference: MLF2™SE
10-0053
Ordering Information
XXXX y K (LF) T
Designation for tape and reel packaging
Lead Free (Optional)
Package Type
K = MLF
Revision Designator (will not correlate with datasheet revision)
Device Type
Example:
95V857AKLFT
0674U01/27/09
12
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