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PDF EV10AQ190 Data sheet ( Hoja de datos )
| Número de pieza | EV10AQ190 | |
| Descripción | Low power QUAD 10-bit 1.25 Gsps ADC operating up to 5 Gsps | |
| Fabricantes | e2v | |
| Logotipo |  |
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EV10AQ190
Datasheet - Preliminary
EV10AQ190
Low power QUAD 10-bit 1.25 Gsps ADC
operating up to 5 Gsps
Main Features
Quad ADC with 10-bit resolution using true e2v single core technology
− 1.25 Gsps Sampling Rate in 4-channel mode
− 2.5 Gsps Sampling Rate in 2-channel mode
− 5 Gsps Sampling Rate in 1-channel mode
− Built-in four-by-four Cross Point Switch
Single 2.5 GHz Differential Symmetrical Input Clock
500 mVpp Analog Input (Differential AC or DC Coupled)
ADC Master Reset (LVDS)
Double Data Rate Output Protocol
LVDS Output format
Digital Interface (SPI) with Reset Signal:
− Channel Mode Selection
− Selectable bandwidth (2 available settings)
− Gain, Offset, Phase Control
− Standby Mode (full or partial)
− Binary or Gray Coding Selection
− Test Modes (ramp, flashing “1”)
Power Supplies: single 3.3V (1.8V Outputs)
Reduced clock induced transients on power supply pins due to BiCMOS Silicon technology
Power Dissipation: 1.4W per channel
EBGA380 Package (RoHS, 1.27 mm Pitch)
Performance
Selectable Full Power Input Bandwidth (-3 dB) up to 3 GHz (4-2-1 channel mode)
Band flatness: ± 0.5 dB from DC to 30% of full Power Input bandwidth
Channel-To-Channel Isolation: > 60 dB
4-channel mode (Fsampling = 1.25 Gsps, -1 dBFS)
− ENOB = 8.8 bit, SFDR = 65 dBc, SNR = 56 dB, DNL = ±0.3 LSB, INL = ±1.5 LSB (Fin= 100 MHz)
− ENOB = 8.5 bit, SFDR = 63 dBc, SNR = 54 dB (Fin= 620 MHz)
− ENOB = 7.8 bit, SFDR = 57 dBc, SNR = 50 dB (Fin= 1.2 GHz)
2-channel mode or 1-channel mode (Fsampling = 2.5 Gsps and 5 Gsps respectively)
− ENOB = 8.7 bit, SFDR = 63 dBc, SNR = 56 dB, DNL = ±0.3 LSB, INL = ±1.5 LSB (Fin= 100 MHz)
− ENOB = 8.4 bit, SFDR = 61 dBc, SNR = 54 dB (Fin= 620 MHz)
− ENOB = 7.7 bit, SFDR = 55 dBc, SNR = 50 dB (Fin= 1.2 GHz)
BER: 10-16 at Full speed
Band flatness: ± 0.5 dB from DC to 30% of full Power Input bandwidth
Low pipe line delay: 4-channel: 9 cycles, 2-channel:9-10 cycles, -channel: 8.5-10 cycles
1
BDC-10/09 – Preliminary
e2v semiconductors SAS 2009
e2v reserves the right to change or modify specifications and features without notice at any time
Free Datasheet http://www.datasheet-pdf.com/
1 page  
EV10AQ190
Figure 7 1-channel mode configuration
CLK
(2.5 GHz)
Clock
Circuit
ADC A
1.25
Gsps
ADC B
1.25
Gsps
In-phase
1.25 GHz
Inverted
1.25 GHz
270° phase -shifted
1.25 GHz
90° phase-shifted
1.25 GHz
ADC C
1.25
Gsps
ADC D
1.25
Gsps
AAI, AAIN or BAI, BAIN or CAI, CAIN or DAI, DAIN
Notes: 1. Refer to Figure 10 ADC Timing in 1-Channel mode
2. For simplification purpose of the timer circuit, the temporary order of ports for sampling is A
C B D, therefore sampling order at output port is as follows:
A: N, N + 4, N + 8, N + 12…
C: N + 1, N + 5, N + 9…
B: N + 2, N + 6, N + 10…
D: N + 3, N + 7, N + 11…
The T/H (Track and Hold) is located after the Cross Point Switch and before the ADC cores. This block
is used to track the data when the internal sampling clock is low and to hold the data when the internal
sampling clock is high. This stage has a gain of 2.
The ADC cores are all the same for the four ADCs. They include a quantifier block as well as a fast
logic block composed of regenerating latches and the Binary/Gray decoding block.
The SPI block provides the digital interface for the digital controls of the ADCs. All the functions of the
ADC are contained in the SPI registers and controlled via this SPI (channel selection, standby mode,
Binary or Gray coding, Offset Gain and Phase adjust..).
The Output buffers are LVDS compatible. They should be terminated using a 100Ω external
termination resistor.
The ADC SYNC buffer is also LVDS compatible. When active, the SYNC signal makes the output
clock signals go low. The output data are undetermined during the reset and until the output clock
restarts.
When the SYNC signal is released, the output clock signals restart after TDR + pipeline delay + a
certain number of input clock cycles which is programmed via the SPI in the SYNC register (from min
delay to min delay + 15 x 2 input clock cycles).
A Diode for the die junction temperature monitoring is implemented using a diode-mounted transistor
but not connected to the die: both cathode and anode are accessible externally.
Eight DACs for the gain and the offset controls are included in the design and are addressed
through the SPI:
- Offset DACs come into play close to the cross point switch;
- Gain DACs come into play on the biasing of the reference ladders of each ADC core.
These DACs have a resolution of 10-bit and will allow the control via the SPI of the offset and gain of
the ADCs:
- Gain adjustment on 1024 steps, ±10% range;
- Offset adjustment on 1024 steps, ±40 mV range (1 step is about 80µV or 0,16 LSB)
5
BDC-10/09 – Preliminary
e2v semiconductors SAS 2009
e2v reserves the right to change or modify specifications and features without notice at any time
Free Datasheet http://www.datasheet-pdf.com/
5 Page 
EV10AQ190
3.5. Transient and Switching Characteristics
Table 6.
Transient and Switching Characteristics
Parameter
TRANSIENT PERFORMANCE
Symbol
Min
Typ
Bit Error Rate
ADC settling time (VIN-VINN = 400 mVpp) in
Full BW mode
Overvoltage recovery time
ADC step response Rise/fall time
(10/90%)
Overshoot
Ringback
BER
TS
ORT
TBD
TBD
TBD
TBD
TBD
Note 1. Output error amplitude < ± 6 lsb. Fs = 1.25 Gsps TJ = 110 °C
Table 7.
Transient and Switching Characteristics
Parameter
Symbol
SWITCHING PERFORMANCE AND CHARACTERISTICS
Clock frequency
Maximum sampling frequency (for each
channel)
FCLK
4-channel mode
2-channel mode
FS
1-channel mode
Minimum clock pulse width (high)
TC1
Minimum clock pulse width (low)
TC2
Aperture Delay
TA
ADC Aperture uncertainty
Jitter
Output rise time for DATA (20%-80%)
TR
Output fall time for DATA (20%-80%)
TF
Output rise time for DATA READY (20%-
80%)
TR
Output fall time for DATA READY (20%-
80%)
TF
Data output delay
TOD
Data Ready output delay
TDR
|TOD-TDR|
Output Data to Data Ready Propagation
Delay
TD1
Min
400
200
400
800
Typ
300
TBD
90
100
90
80
3
3
420
Data Ready to Output Data Propagation
Delay
Data Ready pipeline delay
4-channel mode
2-channel mode
1-channel mode
TD2
TPD
380
TBD
Max
10-16
Unit Note
Error/
sample
ns
ps
ps
%
%
1
Max Unit Note
2500
MHz
1, 2
1250
2500
5000
200
200
50
Msps
Msps
Msps
ps
ps
ps
fs rms
ps
ps
ps
ps
ns
ns
ps
ps
ps
Clock
Cycles
1
1
3
3
4
4
4
5
5
11
BDC-10/09 – Preliminary
e2v semiconductors SAS 2009
e2v reserves the right to change or modify specifications and features without notice at any time
Free Datasheet http://www.datasheet-pdf.com/
11 Page | ||
| Páginas | Total 55 Páginas | |
| PDF Descargar | [ Datasheet EV10AQ190.PDF ] | |
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