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HI-546 Schematic ( PDF Datasheet ) - Intersil Corporation

Teilenummer HI-546
Beschreibung Single 16 and 8/ Differential 8-Channel and 4-Channel CMOS Analog MUXs with Active Overvoltage Protection
Hersteller Intersil Corporation
Logo Intersil Corporation Logo 




Gesamt 15 Seiten
HI-546 Datasheet, Funktion
Data Sheet
HI-546, HI-547, HI-548, HI-549
June 1999 File Number 3150.2
Single 16 and 8, Differential 8-Channel
and 4-Channel CMOS Analog MUXs with
Active Overvoltage Protection
The HI-546, HI-547, HI-548 and HI-549 are analog
multiplexers with active overvoltage protection and
guaranteed rON matching. Analog input levels may greatly
exceed either power supply without damaging the device or
disturbing the signal path of other channels. Active
protection circuitry assures that signal fidelity is maintained
even under fault conditions that would destroy other
multiplexers.
Analog inputs can withstand constant 70VP-P levels with
±15V supplies. Digital inputs will also sustain continuous
faults up to 4V greater than either supply. In addition, signal
sources are protected from short circuiting should
multiplexer supply loss occur. Each input presents 1kof
resistance under this condition. These features make the
HI-546, HI-547, HI-548 and HI-549 ideal for use in systems
where the analog inputs originate from external equipment
or separately powered circuitry. All devices are fabricated
with 44V Dielectrically Isolated CMOS technology. The
HI-546 is a single 16-Channel, the HI-547 is an 8-Channel
differential, the HI-548 is a single 8-Channel and the HI-549
is a 4-Channel differential device. If input overvoltage
protection is not needed the HI-506/507/508/509
multiplexers are recommended. For further information see
Application Notes AN520 and AN521.
For MIL-STD-883 compliant parts, request the HI-546/883,
HI-547/883, HI-548/883 and HI-549/883 datasheets.
Features
• Analog Overvoltage Protection. . . . . . . . . . . . . . . . . . 70VP-P
• No Channel Interaction During Overvoltage
• Guaranteed rON Matching
• Maximum Power Supply . . . . . . . . . . . . . . . . . . . . . . . 44V
• Break-Before-Make Switching
• Analog Signal Range . . . . . . . . . . . . . . . . . . . . . . . . ±15V
• Access Time (Typical) . . . . . . . . . . . . . . . . . . . . . . . 500ns
• Standby Power (Typical) . . . . . . . . . . . . . . . . . . . . . 7.5mW
Applications
• Data Acquisition
• Industrial Controls
• Telemetry
Ordering Information
TEMP.
PART NUMBER RANGE (oC)
PACKAGE
HI1-0546-5
0 to 75 28 Ld CERDIP
HI1-0546-2
-55 to 125 28 Ld CERDIP
HI3-0546-5
0 to 75 28 Ld PDIP
HI4P0546-5
0 to 75 28 Ld PLCC
HI9P0546-9
-40 to 85 28 Ld SOIC
HI1-0547-5
0 to 75 28 Ld CERDIP
HI3-0547-5
0 to 75 28 Ld PDIP
HI4P0547-5
0 to 75 28 Ld PLCC
HI9P0547-9
-40 to 85 28 Ld SOIC
HI1-0548-2
-55 to 125 16 Ld CERDIP
HI1-0548-5
0 to 75 16 Ld CERDIP
HI3-0548-5
0 to 75 16 Ld PDIP
HI4P0548-5
0 to 75 20 Ld PLCC
HI9P0548-5
0 to 75 16 Ld SOIC
HI9P0548-9
-40 to 85 16 Ld SOIC
HI1-0549-2
-55 to 125 16 Ld CERDIP
HI3-0549-5
0 to 75 16 Ld PDIP
HI4P0549-5
0 to 75 20 Ld PLCC
HI9P0549-5
0 to 75 16 Ld SOIC
HI9P0549-9
-40 to 85 16 Ld SOIC
PKG.
NO.
F28.6
F28.6
E28.6
N28.45
M28.3
F28.6
E28.6
N28.45
M28.3
F16.3
F16.3
E16.3
N20.35
M16.15
M16.15
F16.3
E16.3
N20.35
M16.15
M16.15
1 CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
http://www.intersil.com or 407-727-9207 | Copyright © Intersil Corporation 1999






HI-546 Datasheet, Funktion
HI-546, HI-547, HI-548, HI-549
Schematic Diagrams (Continued)
ADDRESS INPUT BUFFER AND LEVEL SHIFTER
TTL REFERENCE
CIRCUIT
V+
VREF
R10
R9
Q1
Q4
D3
GND
LEVEL SHIFTER
P
PP
P
P
P
V+
P
P
OVERVOLTAGE
PROTECTION
V+
D2
P
R1 D1
200
V-
ADD
IN
N
N R2
R3 R4
N NN
N
GND
R5 R7
R6 R8
NN
N
V-
P
LEVEL
SHIFTED
ADDRESS
TO
DECODE
N
6

6 Page









HI-546 pdf, datenblatt
HI-546, HI-547, HI-548, HI-549
Test Circuits and Waveforms TA = 25oC, VSUPPLY = ±15V, VAH = 4V, VAL = 0.8V, VREF = Open, Unless Otherwise Specified (Continued)
VA 50
+4V
A3 HI-546
A2 IN 1
IN 2 THRU
A1 IN 15
A0 IN 16
EN
GND
OUT
1k
+5V
VOUT
50pF
VAH = 4V
0V
50%
ADDRESS
DRIVE (VA)
50%
OUTPUT
Similar connection for HI-547/HI-548/HI-549
FIGURE 7A. TEST CIRCUIT
tOPEN
FIGURE 7B. MEASUREMENT POINTS
VA INPUT
2V/DIV.
S1 ON
S16 ON
OUTPUT
0.5V/DIV.
100ns/DIV.
FIGURE 7C. WAVEFORMS
FIGURE 7. BREAK-BEFORE-MAKE DELAY
A3 HI-546
A2 IN 1
+10V
A1
IN 2 THRU
IN16
A0
EN OUT
VOUT
VA 50GND 1k50pF
Similar connection for HI-547/HI-548/HI-549
FIGURE 8A. TEST CIRCUIT
50%
VAH = 4V
ENABLE DRIVE
50% (VA)
0V
90%
t ON(EN)
OUTPUT
10%
0V
t OFF(EN)
FIGURE 8B. MEASUREMENT POINTS
12

12 Page





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