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ADP1050 Schematic ( PDF Datasheet ) - Analog Devices

Teilenummer ADP1050
Beschreibung Digital Controller
Hersteller Analog Devices
Logo Analog Devices Logo 




Gesamt 30 Seiten
ADP1050 Datasheet, Funktion
Data Sheet
Digital Controller for Isolated
Power Supply with PMBus Interface
ADP1050
FEATURES
GENERAL DESCRIPTION
Versatile digital voltage mode controller
High speed input voltage feedforward control
4 pulse-width modulation (PWM) logic outputs with 625 ps
resolution
Switching frequency: 49 kHz to 625 kHz
Frequency synchronization as slave device
Pulse skipping power saving mode
Prebias startup
Conditional overvoltage protection
Extensive fault detection and protection
PMBus compliant
Graphical user interface (GUI) for ease of programming
On-board EEPROM for programming and data storage
Available in a 20-lead, 4 mm × 4 mm LFCSP
−40°C to +125°C operating temperature
APPLICATIONS
High density, isolated dc-to-dc power supplies
Intermediate bus converters
High availability parallel power systems
Server, storage, industrial, networking, and communications
infrastructure
The ADP1050 is an advanced digital controller with a PMBus
interface targeting high density, high efficiency dc-to-dc power
conversion. This controller implements voltage mode control
with high speed, input voltage feedforward operation for
enhanced transient and noise performance. The ADP1050 has
four programmable pulse-width modulation (PWM) outputs
capable of controlling most high efficiency power supply
topologies, with the added control of synchronous rectification (SR).
The ADP1050 implements several features to enable a robust
system of parallel and redundant operation for customers who
require high availability. The device provides synchronization,
prebias startup, and conditional overvoltage techniques to
identify and safely shut down an erroneous power supply in
parallel operation mode.
The ADP1050 is based on flexible state machine architecture
and is programmed using an intuitive graphical user interface
(GUI). The easy to use GUI reduces design cycle time and
results in a robust, hardware coded system loaded into the built-
in EEPROM. The small size (4 mm × 4 mm) of the LFCSP
package makes the ADP1050 ideal for ultracompact, isolated
dc-to-dc power module or embedded power designs.
TYPICAL APPLICATIONS CIRCUIT
DC
INPUT
LOAD
ADuM3221
ADP3624 or
ADP3654
SR1 SR2
CS1
OUTA
OUTB
VF
ADP1050
OVP VS+ VS–
SYNI/FLGI
RES ADD RTD VCORE
VDD
PG/ALT CTRL SDA SCL AGND
PMBus
Figure 1.
Rev. 0
Document Feedback
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One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
©2014 Analog Devices, Inc. All rights reserved.
Technical Support
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ADP1050 Datasheet, Funktion
ADP1050
Data Sheet
Parameter
RTD TEMPERATURE SENSE PIN
Input Voltage Range
Source Current
Register 0xFE2D = 0xE6
Register 0xFE2D = 0xB0
Register 0xFE2D = 0x80
Register 0xFE2D = 0x40
Register 0xFE2D = 0x00
RTD ADC
Valid Input Voltage Range
ADC Clock Frequency
Register Update Rate
Measurement Resolution
Measurement Accuracy
OTP Digital Comparator
Threshold Accuracy
Comparator Update Speed
Temperature Readings According to
Internal Linearization Scheme
PG/ALT (OPEN-DRAIN) PIN
Output Low Level
CTRL PIN
Input Low Level
Input High Level
Leakage Current
SYNI/FLGI PIN
Input Low Level
Input High Level
Synchronization Range % of Internal Clock
Period
SYNI Positive Pulse Width
SYNI Negative Pulse Width
SYNI Period Drift
Leakage Current
SDA AND SCL PINS
Input Low Voltage
Input High Voltage
Output Low Voltage
Leakage Current
Symbol Min
VIN 0
44.6
38.6
28.6
18.6
9.1
VIN 0
−0.3
−4.8
−2
−80
−0.9
−14.4
−0.5
−8
Typ
46
40
30
20
10
1.56
10
12
10
VOL
VIL
VIH VDD − 0.8
VIL
VIH
tSYNC
VDD − 0.8
90
360
360
VIL
VIH VDD − 0.8
VOL
−5
Max Unit Test Conditions/Comments
1.6 V
47.3 μA
42 μA
31.8 μA
21.6 μA
11 μA
Voltage from RTD to AGND
Factory default setting
1.6
+0.45
+7.2
+2
+80
V
MHz
ms
Bits
% FSR
mV
% FSR
mV
+0.25
+4
+1.1
+17.6
% FSR
mV
% FSR
mV
ms
7 °C
5 °C
2% to 20% of the input voltage range
0% to 100% of the input voltage range
Triggers OT_FAULT flag
T = 85°C with 100 kΩ||16.5 kΩ
T = 100°C with 100 kΩ||16.5 kΩ
Source current is set to 46 µA
(Register 0xFE2D = 0xE6); NTC R25 = 100 kΩ
(1%); beta = 4250 (1%); REXT = 16.5 kΩ (1%)
25°C to 100°C
100°C to 125°C
0.4 V
Sink current = 10 mA
0.4 V
V
1.0 µA
0.4 V
V
110 %
ns
ns
280 ns
1.0 µA
External clock applied on the
SYNI/FLGI pin
External clock applied on the
SYNI/FLGI pin
Period drift between two consecutive
external clocks
0.8 V
V
0.4 V
+5 µA
Sink current = 3 mA
Rev. 0 | Page 6 of 92
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ADP1050 pdf, datenblatt
ADP1050
THEORY OF OPERATION
The ADP1050 is designed as a flexible, easy to use, digital power
supply controller. The ADP1050 integrates the typical functions
that are needed to control a power supply, such as
Output voltage sense and feedback
Voltage feedforward control
Digital loop filter compensation
PWM generation
Current, voltage, and temperature sense
Housekeeping and I2C/PMBus interface
Calibration and trimming
The main function of controlling the output voltage is performed
by the feedback ADCs, the digital loop compensator, and the
digital PWM engine.
The feedback ADCs feature a patented multipath architecture,
with a high speed, low resolution (fast and coarse) ADC and a
low speed, high resolution (slow and accurate) ADC. The ADC
outputs are combined to form a high speed and high resolution
feedback path. Loop compensation is implemented using the
digital compensator. This proportional, integral, derivative (PID)
compensator is implemented in the digital domain to allow easy
programming of filter characteristics, which is of great value in
customizing and debugging designs. The PWM engine generates
CS1 VF
Data Sheet
up to four programmable PWM outputs for control of primary
side FET drivers and synchronous rectification FET drivers. This
programmability allows many generic and specific switching
power supply topologies to be realized.
Conventional power supply housekeeping features, such as input
voltage sense, output voltage sense, primary side current sense,
and secondary side current sense, are included. An extensive set
of protections is included, such as overvoltage protection (OVP),
overcurrent protection (OCP), overtemperature protection (OTP),
and undervoltage protection (UVP).
These features are programmable through the I2C/PMBus
digital bus interface. This interface is also used for calibrations.
Other information, such as input current, output current, and
fault flags, is also available through this digital bus interface.
The internal EEPROM can store all programmed values and allows
standalone control without a microcontroller. A free, downloadable
GUI is available that provides all the necessary software to program
the ADP1050. To obtain the latest GUI software and a user guide,
visit http://www.analog.com/digitalpower.
The ADP1050 operates from a single 3.3 V power supply and is
specified from −40°C to +125°C.
VS+ VS–
OUTA
OUTB
SR1
SR2
ADC
ADC
PWM
ENGINE
DIGITAL CORE
8kB
EEPROM
PMBus
ADC
VREF
DAC
ADC
OSC
UVLO
LDO
OVP
RTD
ADD
RES
AGND
VDD
SYNI/FLGI SCL SDA CTRL
PG/ALT VCORE
Figure 10. Functional Block Diagram
Rev. 0 | Page 12 of 92
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