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PDF SI1015 Data sheet ( Hoja de datos )
| Número de pieza | SI1015 | |
| Descripción | (SI1010 - SI1015) Ultra Low Power ADC | |
| Fabricantes | Silicon Laboratories | |
| Logotipo |  |
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Si1010/1/2/3/4/5
Ultra Low Power, 16/8 kB, 12/10-Bit ADC
MCU with Integrated 240–960 MHz EZRadioPRO® Transceiver
Ultra Low Power: 0.9 to 3.6 V Operation
- Typical sleep mode current < 0.1 µA; retains state and
RAM contents over full supply range; fast wakeup of < 2 µs
- Less than 600 nA with RTC running
- Less than 1 µA with RTC running and radio state retained
- On-chip dc-dc converter allows operation down to 0.9 V.
- Two built-in brown-out detectors cover sleep and active
modes
10-Bit or 12-Bit Analog to Digital Converter
- Up to 300 ksps
- Up to 18 external inputs
- External pin or internal VREF (no external capacitor
required)
- Built-in temperature sensor
- External conversion start input option
- Autonomous burst mode with 16-bit automatic averaging
accumulator
Dual Comparators
- Programmable hysteresis and response time
- Configurable as interrupt or reset source
- Low current (< 0.5 µA)
On-Chip Debug
- On-chip debug circuitry facilitates full-speed, non-intrusive
in-system debug (No emulator required)
- Provides breakpoints, single stepping
- Inspect/modify memory and registers
- Complete development kit
High-Speed 8051 µC Core
- Pipelined instruction architecture; executes 70% of instruc-
tions in 1 or 2 system clocks
- Up to 25 MIPS throughput with 25 MHz clock
- Expanded interrupt handler
Memory
- 768 bytes RAM 16 kB (Si1010/2/4) or 8 kB (Si1011/3/5)
Flash; In-system programmable
EZRadioPRO® Transceiver
- Frequency range = 240–960 MHz
- Sensitivity = –121 dBm
- FSK, GFSK, and OOK modulation
- Max output power = +20 dBm (Si1010/1), +13 dBm
(Si1012/3/4/5)
- RF power consumption
- 18.5 mA receive
- 18 mA @ +1 dBm transmit
- 30 mA @ +13 dBm transmit
- 85 mA @ +20 dBm transmit (Si1010/1)
- Data rate = 0.123 to 256 kbps
- Auto-frequency calibration (AFC)
- Antenna diversity and transmit/receive switch control
- Programmable packet handler
- TX and RX 64 byte FIFOs
- Frequency hopping capability
- On-chip crystal tuning
Digital Peripherals
- 12 port I/O plus 3 GPIO pins; Hardware enhanced UART,
SPI, and I2C serial ports available concurrently
- Low power 32-bit SmaRTClock
- Four general purpose 16-bit counter/timers; six channel
programmable counter array (PCA)
Clock Sources
- Precision internal oscillators: 24.5 MHz with ±2% accuracy
supports UART operation; spread-spectrum mode for
reduced EMI; Low power 20 MHz internal oscillator
- External oscillator: Crystal, RC, C, CMOS clock
- SmaRTClock oscillator: 32.768 kHz crystal or self-oscillate
- Can switch between clock sources on-the-fly; useful in
power saving modes and in implementing various power
saving modes
Package
- 42-pin LGA (5 x 7 mm)
Temperature Range: –40 to +85 °C
Rev. 1.2 4/13
ANALOG
DIGITAL I/O
PERIPHERALS
A 12/10-bit
M 75/300 ksps
IREF
U ADC
X
++
TEMP
SENSOR
VREF
–
–
VREG VOLTAGE
COMPARATORS
UART
SMBus
SPI
PCA
Timer 0
Timer 1
Timer 2
Timer 3
CRC
Port 0
EZRadio
PRO
Serial
Interface
Port 1
Port 2
24.5 MHz PRECISION
INTERNAL OSCILLATOR
20 MHz LOW POWER
INTERNAL OSCILLATOR
External Oscillator
HARDWARE smaRTClock
HIGH-SPEED CONTROLLER CORE
16/8 kB
ISP FLASH
FLEXIBLE
INTERRUPTS
8051 CPU
(25 MIPS)
DEBUG
CIRCUITRY
768 B SRAM
POR WDT
EZRadioPRO
(240–960 MHz)
LNA
Mixer
PGA
ADC
PA
Digital
Modem
Delta
Sigma
Modulator
Digital
Logic
PLL
OSC
Copyright © 2013 by Silicon Laboratories
Si1010/1/2/3/4/5
Free Datasheet http://www.datasheet4u.net/
1 page  
Si1010/1/2/3/4/5
18.8. SmaRTClock (Real Time Clock) Reset ......................................................... 193
18.9. Software Reset .............................................................................................. 193
19. Clocking Sources................................................................................................. 195
19.1. Programmable Precision Internal Oscillator .................................................. 196
19.2. Low Power Internal Oscillator........................................................................ 196
19.3. External Oscillator Drive Circuit..................................................................... 196
19.3.1. External Crystal Mode........................................................................... 196
19.3.2. External RC Mode................................................................................. 198
19.3.3. External Capacitor Mode....................................................................... 199
19.3.4. External CMOS Clock Mode ................................................................. 199
19.4. Special Function Registers for Selecting and Configuring the
System Clock................................................................................................. 200
20. SmaRTClock (Real Time Clock).......................................................................... 204
20.1. SmaRTClock Interface .................................................................................. 204
20.1.1. SmaRTClock Lock and Key Functions.................................................. 205
20.1.2. Using RTC0ADR and RTC0DAT to Access SmaRTClock
Internal Registers.................................................................................. 205
20.1.3. RTC0ADR Short Strobe Feature........................................................... 206
20.1.4. SmaRTClock Interface Autoread Feature ............................................. 206
20.1.5. RTC0ADR Autoincrement Feature........................................................ 207
20.2. SmaRTClock Clocking Sources .................................................................... 210
20.2.1. Using the SmaRTClock Oscillator with a Crystal or
External CMOS Clock ........................................................................... 210
20.2.2. Using the SmaRTClock Oscillator in Self-Oscillate Mode..................... 211
20.2.3. Using the Low Frequency Oscillator (LFO) ........................................... 211
20.2.4. Programmable Load Capacitance......................................................... 211
20.2.5. Automatic Gain Control (Crystal Mode Only) and SmaRTClock
Bias Doubling ........................................................................................ 212
20.2.6. Missing SmaRTClock Detector ............................................................. 213
20.2.7. SmaRTClock Oscillator Crystal Valid Detector ..................................... 214
20.3. SmaRTClock Timer and Alarm Function ....................................................... 214
20.3.1. Setting and Reading the SmaRTClock Timer Value ............................. 214
20.3.2. Setting a SmaRTClock Alarm ............................................................... 214
20.3.3. Software Considerations for using the SmaRTClock
Timer and Alarm ................................................................................... 215
21. Port Input/Output ................................................................................................. 220
21.1. Port I/O Modes of Operation.......................................................................... 221
21.1.1. Port Pins Configured for Analog I/O...................................................... 221
21.1.2. Port Pins Configured For Digital I/O...................................................... 221
21.1.3. Interfacing Port I/O to 5 V and 3.3 V Logic............................................ 222
21.1.4. Increasing Port I/O Drive Strength ........................................................ 222
21.2. Assigning Port I/O Pins to Analog and Digital Functions............................... 222
21.2.1. Assigning Port I/O Pins to Analog Functions ........................................ 222
21.2.2. Assigning Port I/O Pins to Digital Functions.......................................... 223
21.2.3. Assigning Port I/O Pins to External Digital Event Capture Functions ... 223
Rev. 1.2
5
Free Datasheet http://www.datasheet4u.net/
5 Page 
Si1010/1/2/3/4/5
Figure 5.9. Temperature Sensor Error with 1-Point Calibration (VREF = 1.68 V) .... 97
Figure 5.10. Voltage Reference Functional Block Diagram ..................................... 99
Figure 7.1. Comparator 0 Functional Block Diagram ............................................ 104
Figure 7.2. Comparator 1 Functional Block Diagram ............................................ 105
Figure 7.3. Comparator Hysteresis Plot ................................................................ 106
Figure 7.4. CPn Multiplexer Block Diagram ........................................................... 111
Figure 8.1. CIP-51 Block Diagram ......................................................................... 114
Figure 9.1. Si1010/1/2/3/4/5 Memory Map ............................................................ 123
Figure 9.2. Flash Program Memory Map ............................................................... 124
Figure 13.1. Flash Program Memory Map (16 kB and 8 kB devices) .................... 148
Figure 14.1. Si1010/1/2/3/4/5 Power Distribution .................................................. 158
Figure 15.1. CRC0 Block Diagram ........................................................................ 166
Figure 15.2. Bit Reverse Register ......................................................................... 174
Figure 16.1. DC-DC Converter Block Diagram ...................................................... 175
Figure 16.2. DC-DC Converter Configuration Options .......................................... 178
Figure 18.1. Reset Sources ................................................................................... 187
Figure 18.2. Power-Fail Reset Timing Diagram .................................................... 188
Figure 18.3. Power-Fail Reset Timing Diagram .................................................... 189
Figure 19.1. Clocking Sources Block Diagram ...................................................... 195
Figure 19.2. 25 MHz External Crystal Example ..................................................... 197
Figure 20.1. SmaRTClock Block Diagram ............................................................. 204
Figure 20.2. Interpreting Oscillation Robustness (Duty Cycle) Test Results ......... 213
Figure 21.1. Port I/O Functional Block Diagram .................................................... 220
Figure 21.2. Port I/O Cell Block Diagram .............................................................. 221
Figure 21.3. Crossbar Priority Decoder with No Pins Skipped .............................. 225
Figure 21.4. Crossbar Priority Decoder with Crystal Pins Skipped ....................... 226
Figure 22.1. EZRadioPRO Serial Interface Block Diagram ................................... 240
Figure 22.2. SPI Timing ......................................................................................... 242
Figure 22.3. SPI Timing—READ Mode ................................................................. 242
Figure 22.4. SPI Timing—Burst Write Mode ......................................................... 243
Figure 22.5. SPI Timing—Burst Read Mode ......................................................... 243
Figure 22.6. Master Mode Data/Clock Timing ....................................................... 244
Figure 22.7. SPI Master Timing ............................................................................. 249
Figure 23.1. State Machine Diagram ..................................................................... 252
Figure 23.2. TX Timing .......................................................................................... 255
Figure 23.3. RX Timing .......................................................................................... 256
Figure 23.4. Frequency Deviation ......................................................................... 259
Figure 23.5. Sensitivity at 1% PER vs. Carrier Frequency Offset ......................... 261
Figure 23.6. FSK vs. GFSK Spectrums ................................................................. 263
Figure 23.7. Direct Synchronous Mode Example .................................................. 266
Figure 23.8. Direct Asynchronous Mode Example ................................................ 266
Figure 23.9. Microcontroller Connections .............................................................. 267
Figure 23.10. PLL Synthesizer Block Diagram ...................................................... 269
Figure 23.11. FIFO Thresholds ............................................................................. 272
Figure 23.12. Packet Structure .............................................................................. 273
Rev. 1.2
11
Free Datasheet http://www.datasheet4u.net/
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet SI1015.PDF ] | |
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