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PDF MST705 Data sheet ( Hoja de datos )
| Número de pieza | MST705 | |
| Descripción | Small Size LCD TV Processor | |
| Fabricantes | Mstar | |
| Logotipo |  |
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Hay una vista previa y un enlace de descarga de MST705 (archivo pdf) en la parte inferior de esta página. Total 70 Páginas | ||
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MST705
Small Size LCD TV Processor with Video Decoder
Preliminary Data Sheet Version 0.1
FEATURES
n Video Decoder
n Color Engine
Ÿ Supports NTSC, PAL and SECAM video input
Ÿ Brightness, contrast, saturation, and hue
formats
adjustment
Ÿ 2D NTSC and PAL comb-filter for Y/C
Ÿ 9-tap programmable multi-purpose FIR (Finite
separation of CVBS input
Impulse Response) filter
Ÿ Multiple CVBS and S-video inputs
Ÿ Differential 3-band peaking engine
Ÿ ACC, AGC, and DCGC (Digital Chroma Gain
Ÿ Luminance Transient Improvement (LTI)
Control)
Ÿ Chrominance Transient Improvement (CTI)
n Analog Input
Ÿ Black Level Extension (BLE)
Ÿ Supports RGB input format from PC,
Ÿ White Level Extension (WLE)
camcorders and GPS
Ÿ Favor Color Compensation (FCC)
Ÿ Supports YCbCr inputs from conventional video
Ÿ 3-channel gamma curve adjustment
source and HDTV
n Scaling Engine/Panel Interface
Ÿ Supports video input 480i, 480p, 576i, 576p,
Ÿ Supports LVDS panel up to 1366x768
720p, 1080i; 1080P; RGB input resolution in
Ÿ Supports TTL/TCON and analog TCON panel
640x480, 800x480, and 800x600, 1024x768,
1280x1024
Mstar ConfidentialŸ 3-channel low-power 10-bit ADCs integration
Ÿ Supports single 8-bit TTL panel output
Ÿ Supports various displaying modes
Ÿ Supports horizontal panorama scaling
forfor YCbCr and RGB
Ÿ Supports RGB composite sync input (CSYNC),
SOY, SOG, HSYNC, and VSYNC
n Miscellaneous
Ÿ Built-in MCU
Ÿ Supports CCIR656 digital input
Ÿ On-chip clock synthesizer and PLL
Ÿ Auto-position adjustment, auto-phase
Internal Use Onlyadjustment, auto-gain adjustment, and
Ÿ Built-in internal OSD with 256 programmable
fonts, 16-color palettes, and 12-bit color
resolution
auto-mode detection
Ÿ Spread spectrum clocks
Ÿ 3.3V output pads with programmable driving
current
Ÿ 100-pin LQFP package
-1-
Copyright © 2010 MStar Semiconductor, Inc. All rights reserved.
11/2/2010
Free Datasheet http://www.datasheet4u.net/
1 page  
MST705
Small Size LCD TV Processor with Video Decoder
Preliminary Data Sheet Version 0.1
PIN DESCRIPTION
Analog Panel Output Interface
Pin Name
DAC_VR
DAC_VG
DAC_VB
VREP_DAC
VCOMOUT
Pin Type
Analog Output
Analog Output
Analog Output
Analog Input
Analog Output
Function
Red Channel Output 3.0 Vp-p
Green Channel Output 3.0 Vp-p
Blue Channel Output 3.0 Vp-p
DAC Top Reference Voltage Decoupling Cap. 1uF to
Ground
Pulse Output for Common Voltage.
Pin
76
77
79
80
81
Analog Interface
Pin Name
Pin Type
Function
BIN0/PBIN0
Analog Input
Analog Blue Input from Channel 0
SOG0
Mstar ConfidentialGIN0/YIN0
Analog Input
Analog Input
Sync On Green Signal Input from Channel 0
Analog Green Input from Channel 0
forRGBINM0
RIN0/PRIN0
HSYNCIN
Analog Input
Reference Ground for Analog Green Input from Channel 0
Analog Input
Analog Red Input from Channel 0
Schmitt Trigger Input HSYNC / Composite Sync for VGA Input
Internal Use OnlyVSYNCIN
w/ 5V-tolerant
Schmitt Trigger Input VSYNC for VGA Input
w/ 5V-tolerant
BIN1/PBIN1
Analog Input
Analog Blue Input from Channel 1
RGBINM1
Analog Input
Reference Ground for Analog Green Input from Channel 1
GIN1/YIN1
Analog Input
Analog Green Input from Channel 1
SOG1
Analog Input
Sync On Green Signal Input from Channel 1
RIN1/PRIN1
Analog Input
Analog Red Input from Channel 1
VCOM0
Analog Input
Common Analog Input Reference Ground 0
CVBS1/SC0
Analog Input
CVBS0 or S-Video (Y/C) Input Channel 0
CVBS2/SY0
Analog Input
CVBS1 or S-Video (Y/C) Input Channel 0
CVBS3/SC1
Analog Input
CVBS2 or S-Video (Y/C) Input Channel 1
CVBS4/SY1
Analog Input
CVBS3 or S-Video (Y/C) Input Channel 1
Pin
2
3
4
5
6
7
8
10
11
12
13
14
15
16
17
18
19
-5-
Copyright © 2010 MStar Semiconductor, Inc. All rights reserved.
11/2/2010
Free Datasheet http://www.datasheet4u.net/
5 Page 
MST705
Small Size LCD TV Processor with Video Decoder
Preliminary Data Sheet Version 0.1
REGISTER DESCRIPTION
General Control Register
General Control Register
Index Name
Bits Description
00h REGBK
7:0 Default : 0x00
Access : R/W
XTAL_OK (RO)
7 Crystal ready.
MCU_SEL (RO)
6 0: Embedded MCU.
1: External serial bus interface.
- 5:4 Reserved.
AINC
3 Serial bus address auto Increase.
0: Enable.
1: Disable.
- 2 Reserved.
Mstar ConfidentialREGBK[1:0]
1:0 Register Bank Select.
00: Register of scaler.
01: Register of ADC/ACE/MCU.
for
REGBK[2:0]
2:0
Internal
10: Register of Video Decoder Front End (VFE).
11: Register of Video Decoder 2D Comb Filter (VCF).
Register Bank Select.
Use Only000: Register of scaler.
001: Register of ADC/ACE/MCU.
010: Register of Video Decoder Front End (VFE).
011: Register of Video Decoder 2D Comb Filter (VCF).
100: Register of LVDS/DPWM.
01h ~ -
FFh -
7:0 Default : -
7:0 Reserved.
Access : -
- 11 -
Copyright © 2010 MStar Semiconductor, Inc. All rights reserved.
11/2/2010
Free Datasheet http://www.datasheet4u.net/
11 Page | ||
| Páginas | Total 70 Páginas | |
| PDF Descargar | [ Datasheet MST705.PDF ] | |
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