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TW2834 Schematic ( PDF Datasheet ) - Intersil

Teilenummer TW2834
Beschreibung 4 Channel Video QUAD/MUX Controller
Hersteller Intersil
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Gesamt 30 Seiten
TW2834 Datasheet, Funktion
TW2834
4 Channel Video QUAD/MUX Controller
For Security Applications
Preliminary Data Sheet from Techwell, Inc.
Information may change without notice
February 1, 2011
FN7739.0
1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774 | Copyright Intersil Americas Inc. 2011. All Rights Reserved
Intersil (and design) is a trademark owned by Intersil Corporation or one of its subsidiaries.
All other trademarks mentioned are the property of their respective owners.
Free Datasheet http://www.datasheet4u.net/






TW2834 Datasheet, Funktion
TW2834
Introduction
The TW2834 has four high quality NTSC/PAL video decoders, dual color display controllers and
dual video encoders. The TW2834 contains four built-in analog anti-aliasing filters, four 10bit
Analog-to-Digital converters, proprietary digital gain/clamp controller, high quality Y/C separator to
reduce cross-noise and high performance free scaler. Four built-in motion and blind detectors can
increase the feature of security system. The TW2834 has flexible video display controller including
basic QUAD and MUX functions. The TW2834 also has excellent graphic overlay function that
displays character/bitmap for OSD, single box, 2D array box, and mouse pointer. The built-in
channel ID CODEC allows auto decoding and displaying during playback and the additional scaler
on the playback supports multi-cropping function of the same field or frame image. The TW2834
contains two video encoders with four 10bit Digital-to-Analog converters for providing 2 composite
or S-video. The TW2834 also can be extended up to 8/16 channel video controller using chip-to-
chip cascade connection.
Features
Four Video Decoders
Accepts all NTSC/PAL standard formats with auto detection
Integrated four analog anti-aliasing filters and four 10 bit CMOS ADCs
High performance adaptive comb filters for all NTSC/PAL standards
IF compensation filter for improvement of color demodulation
PAL delay lines for correcting PAL phase errors
Programmable hue, saturation, contrast, brightness and sharpness
High performance horizontal and vertical scaler for each path including playback input
Fast video locking system for non-realtime application
Four built-in motion detectors with 16X12 cells and blind detectors
Additional digital input for playback with ITU-R BT.656 standard
Auto cropping / strobe for playback input with Channel ID decoder
Supports four channel full D1 record and playback mode
Dual Video Controllers
Full Live/Strobe/Switch function
Various channel attribute control
Supports pseudo 8 Channel or Dual page mode
Horizontal / Vertical Mirroring for each channel
Last image capture when video-loss detected
6 FN7739.0
February 1, 2011
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6 Page









TW2834 pdf, datenblatt
TW2834
Memory Interface Pins
Name
DATAX[15:0]
ADDRX[12:0]
Number
50,51,54,
55,56,58,
59,60,62,
63,64,66,
67,68,70,
71
23,24,26,
27,29,30,
31,33,34,
35,37,38,
39
BA1X
41
BA0X
RASBX
CASBX
WEBX
DQMX
42
43
45
46
47
CLK54MEMX
DATAY[15:0]
ADDRY[10:0]
BA0Y
49
97,98,99,
101,102,103,
106,107,108,
110,111,112,
114,115,116,
118
74,75,76,
78,79,81,
82,83,85,
86,87
89
RASBY
90
CASBY
91
WEBY
93
DQMY
94
CLK54MEMY
95
Type
Description
I/O SDRAM data bus of display path.
SDRAM address bus of display path.
O
ADDRX[10] is AP.
ADDRX[12] can be used for PBIN 2 clock.
ADDRX[11] can be used for PBIN 1 clock.
O
SDRAM bank1 selection of display path or
Can be used for PBIN 3 clock.
O SDRAM bank0 selection of display path.
O SDRAM row address selection of display path.
O SDRAM column address selection of display path
O SDRAM write enable of display path.
O SDRAM write mask of display path.
O
SDRAM clock of display path.
Clock phase/frequency is controlled via register.
I/O
SDRAM data bus of record path or
PBIN 2 and PBIN 3 input.
SDRAM address bus of record path.
O
ADDRY[10] is AP. or
ADDRY[10:3] is Decoder Bypass output 1/3.
ADDRY[2:0] is Decoder Bypass output 0/2 [7:5].
O
SDRAM Bank0 Selection of record path or
Decoder Bypass output 0/2 [4].
O
SDRAM row address selection of record path or
Decoder Bypass output 0/2 [3].
O
SDRAM column address selection of record path
or Decoder Bypass output 0/2 [2].
O
SDRAM write enable of record path or
Decoder Bypass output 0/2 [1].
O
SDRAM write mask of record path or
Decoder Bypass output 0/2 [0]
O
SDRAM clock of record path.
Clock phase/frequency is controlled via register.
12
FN7739.0
February 1, 2011
Free Datasheet http://www.datasheet4u.net/

12 Page





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