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CMX602A Schematic ( PDF Datasheet ) - CML

Teilenummer CMX602A
Beschreibung Calling Line Identifier
Hersteller CML
Logo CML Logo 




Gesamt 25 Seiten
CMX602A Datasheet, Funktion
CML Semiconductor Products
Calling Line Identifier
plus Call Waiting (Type II) CMX602A
D/602A/4 February 1998
Provisional Issue
Features
CLI and CIDCW System Operation
Low Power Operation 0.5mA at 2.7V
Zero-Power Ring or Line Reversal
Detector
FSK Demodulator with Data Retiming
High Sensitivity CAS Tone Detection
Low CAS Tone Falsing in CIDCW Mode
Applications
CLI and CIDCW Adjunct Boxes
CLI and CIDCW Feature Phones
Bellcore, ETSI, British Telecom and
Mercury Systems
Computer Telephone Integration
Call Logging Systems
Voice-Mail Equipment
1.1 Brief Description
The CMX602A is a low power CMOS integrated circuit for the reception of the physical layer signals used in
BT's Calling Line Identification Service (CLIP), Bellcore's Calling Identity Delivery System (CID), the Cable
Communications Association's Caller Display Services (CDS), and similar evolving systems. It also meets the
requirements of emerging Caller Identity with Call Waiting services (CIDCW).
The device includes a 'zero-power' ring or line reversal detector, a dual-tone (2130Hz plus 2750Hz) Tone Alert
Signal and a 1200-baud FSK V23/Bell202 compatible asynchronous data demodulator with a data retiming
circuit which removes the need for a UART in the associated µController.
It is suitable for use in systems to BT specifications SIN227 and SIN242, Bellcore GR-30-CORE and SR-TSV-
002476, CCA TW/P&E/312, ETSI ETS 300 659 parts 1 and 2, ETS 300 778 parts 1 and 2 and Mercury
Communications MNR 19.
© 1998 Consumer Microcircuits Limited
Free Datasheet http://www.datasheet4u.com/






CMX602A Datasheet, Funktion
Calling Line Identifier
1.4 External Components
CMX602A
R1
R2
R3, R4, R5
R6, R7
R8
R9
R10
R11
470k
See section 1.5.8
470k
470k
470kfor VDD = 3.3V
680kfor VDD = 5.0V
(See section 1.5.2)
240kfor VDD = 3.3V
200kfor VDD = 5.0V
(See section 1.5.2)
160k
100kΩ ±20%
C1, C2
C3, C4
C5
C6, C7
C8,C9
18pF
0.1µF
0.33µF
680pF
0.1µF
X1
D1 - D4
3.579545MHz
1N4004
Resistors ±1%, capacitors ±20% unless otherwise stated.
Figure 2 Recommended External Components for Typical Application
It is recommended that the printed circuit board is laid out with a ground plane in the CMX602A area to provide
a low impedance ground connection to the VSS pin and to the decoupling capacitors C8 and C9.
© 1998 Consumer Microcircuits Limited
6
D/602A/4
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6 Page









CMX602A pdf, datenblatt
Calling Line Identifier
CMX602A
When no signal is present on the telephone line, RD will be at VSS and RT pulled to VDD by R5 so the output of
the Schmitt trigger 'B' will be low.
The ring signal is usually applied at the subscriber's exchange as an ac voltage inserted in series with one of
the telephone wires and will pass through either C3 and R3 or C4 and R4 to appear at the top end of R1 (point
X in Figure 7) in a rectified and attenuated form.
The signal at point X will be further attenuated by the potential divider formed by R1 and R2 before being
applied to the CMX602A input RD . If the amplitude of the signal appearing at RD is greater than the input
threshold (Vthi) of Schmitt trigger 'A' then the N transistor connected to RT will be turned on, pulling the voltage
at RT to VSS by discharging the external capacitor C5. The output of the Schmitt trigger 'B' will then go high,
activating the DET and/or IRQN outputs depending on the states of the MODE and ZP inputs.
The minimum amplitude ringing signal that is certain to be detected is
( 0.7 + Vthi x [R1 + R2 + R3] / R2 ) x 0.707 Vrms
where Vthi is the high-going threshold voltage of the Schmitt trigger A (see section 1.7).
With R1, R3 and R4 all 470kas Figure 2, then setting R2 to 68kwill guarantee detection of ringing signals
of 40Vrms and above for VDD over the range 2.7 to 5.5V.
A line polarity reversal may be detected using the same circuit but there will be only one pulse at RD. The BT
specification SIN242 says that the circuit must detect a +15V to -15V reversal between the two lines slewing in
30ms. For a linearly changing voltage at the input to C3 (or C4), then the voltage appearing at the RD pin will
be
dV/dt x C3 x [ 1 - exp(-t/T) ] x R2
where T = C3 x (R1 + R2 + R3) and dV/dt is the input slew rate.
For dV/dt = 500V/sec (15V in 30ms), R1, R3 and R4 all 470kand C3, C4 both 0.1µF as Figure 2, then setting
R2 to 390kwill guarantee detection at VDD = 5.5V.
If the time constant of R5 and C5 is large enough then the voltage on RT will remain below the threshold of the
'B' Schmitt trigger keeping the DET and/or IRQN outputs active for the duration of a ring cycle
The time for the voltage on RT to charge from VSS towards VDD can be derived from the formula
VRT = VDD x [1 - exp(-t/(R5 x C5)) ]
As the Schmitt trigger high-going input threshold voltage (Vthi) has a minimum value of 0.56 x VDD , then the
Schmitt trigger B output will remain high for a time of at least 0.821 x R5 x C5 following a pulse at RD.
Using the values given in Figure 2 (470kand 0.33µF) gives a minimum time of 100 ms (independent of VDD ),
which is adequate for ring frequencies of 10Hz or above.
If necessary, the µC can distinguish between a ring and a reversal by timing the length of the IRQN or DET
output.
© 1998 Consumer Microcircuits Limited
12
D/602A/4
Free Datasheet http://www.datasheet4u.com/

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