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BJ8P153 Schematic ( PDF Datasheet ) - ETC

Teilenummer BJ8P153
Beschreibung (BJ8P153 / BJ8P508) 8-BIT MICRO-CONTROLLER
Hersteller ETC
Logo ETC Logo 




Gesamt 54 Seiten
BJ8P153 Datasheet, Funktion
BJ8P508/153
OTP ROM
BJ8P508/153
8-BIT MICRO-CONTROLLER
Version 2.0
Free Datasheet http://www.datasheet4u.com/






BJ8P153 Datasheet, Funktion
3. PIN ASSIGNMENTS
BJ8P508/153
OTP ROM
Table 1. pin description
Symbol
Vdd
Type
-
P65/OSCI
I/O
P64/OSCO
I/O
P63//RESET
I
P62/TCC
P61
P60//INT
I/O
I/O
I/O
FIG1.pin assignments
Function
Power supply
*General purpose I/O pin.
*External clock signal input.
*Input pin of XT oscillator.
*Pull-high/open-drain
*Wake up from sleep mode when the status of the pin changes.
*General purpose I/O pin.
*External clock signal input.
*Input pin of XT oscillator
*Pull-high/open-drain
*Wake up from sleep mode when the status of the pin changes.
*If set as /RESET and remain at logic low,the device will be uder
reset.
*Wake up from sleep mode when the status of the pin changes.
*Voltage on/RESET must not exceed Vdd during the normal mode.
*Internal Pull-high is on if defined as /RESET.
*P63 is input pin only.
*General purpose I/O pin.
*Pull-high/open-drain/pull-down.
*Wake up from sleep mode when the status of the pin changes.
*Schmitt Trigger input during the programming mode.
*General purpose I/O pin.
*Pull-high/open-drain/pull-down.
*Wake up from sleep mode when the status of the pin changes.
*Schmitt Trigger input during the programming mode.
*General purpose I/O pin.
*Pull-high/open-drain/pull-down.
*Wake up from sleep mode when the status of the pin changes.
*Schmitt Trigger input during the programming mode.
*External interrupt pin triggered by falling edge.
This specification is subject to change without prior notice.
6
6.17.2007 (V2.0)
Free Datasheet http://www.datasheet4u.com/

6 Page









BJ8P153 pdf, datenblatt
BJ8P508/153
OTP ROM
• RF can be cleared by instruction but cannot be set.
• IOCF is the interrupt mask register.
• Note that the result of reading RF is the "logic AND" of RF and IOCF.
8. R10 ~ R2F
• All of these are the 8-bit general-purpose registers.
4.2 Special Purpose Registers
1. A (Accumulator)
• Internal data transfer, or instruction operand holding
• It cannot be addressed.
2. CONT (Control Register)
765 432 1
-
INT
TS
TE
PAB
PSR2
PSR1
Bit 7 Not used.
Bit 6 (INT) Interrupt enable flag
0: masked by DISI or hardware interrupt
1: enabled by ENI/RETI instructions
Bit 5 (TS) TCC signal source
0: internal instruction cycle clock, P62 is a bi-directional I/O pin.
1: transition on TCC pin
Bit 4 (TE) TCC signal edge
0: increment if the transition from low to high takes place on TCC pin
1: increment if the transition from high to low takes place on TCC pin
Bit 3 (PAB) Prescaler assignment bit.
0: TCC
1: WDT
Bit 2 (PSR2) ~ 0 (PSR0) TCC/WDT prescaler bits.
PSR2 PSR1 PSR0
TCC Rate
00 0
00 1
01 0
01 1
10 0
10 1
11 0
11 1
1:2
1:4
1:8
1:16
1:32
1:64
1:128
1:256
WDT Rate
1:1
1:2
1:4
1:8
1:16
1:32
1:64
1:128
0
PSR0
This specification is subject to change without prior notice.
12
6.17.2007 (V2.0)
Free Datasheet http://www.datasheet4u.com/

12 Page





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