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ADRF6820 Schematic ( PDF Datasheet ) - Analog Devices

Teilenummer ADRF6820
Beschreibung Quadrature Demodulator
Hersteller Analog Devices
Logo Analog Devices Logo 




Gesamt 30 Seiten
ADRF6820 Datasheet, Funktion
Data Sheet
695 MHz to 2700 MHz, Quadrature Demodulator
with Integrated Fractional-N PLL and VCO
ADRF6820
FEATURES
I/Q demodulator with integrated fractional-N PLL
RF input frequency range: 695 MHz to 2700 MHz
Internal LO frequency range: 356.25 MHz to 2850 MHz
Input P1dB: 14.5 dBm at 1900 MHz RF
Input IP3: 37 dBm at 1900 MHz RF
Programmable HD3/IP3 trim
Single pole, double throw (SPDT) RF input switch
RF digital step attenuation range: 0 dB to 15 dB
Integrated RF tunable balun for single-ended 50 Ω input
Multicore integrated VCO
Demodulated 1 dB bandwidth: 600 MHz
4 selectable baseband gain and bandwidth modes
Digital programmable LO phase offset and dc nulling
Programmable via 3-wire serial port interface (SPI)
40-lead, 6 mm × 6 mm LFCSP
APPLICATIONS
Cellular W-CDMA/GSM/LTE
Digital predistortion (DPD) receivers
Microwave point-to-point radios
FUNCTIONAL BLOCK DIAGRAM
RFIN0 29
15 14 13
SERIAL PORT
INTERFACE
RFIN1 22
2 3 8 9 23 25 26 28 38
DC/PHASE
CORRECTION
4 I+
5 I–
POLYPHASE
FILTER
QUAD
DIVIDER
35 LOIN+
34 LOIN–
PLL 39 REFIN
LDO
2.5V
LDO
VCO
1 19 30 36 31
VPOS_3P3
DC/PHASE
CORRECTION
27 33 40 10
DECL1 TO
DECL4
Figure 1.
11 21
VPOS_5V
6 Q–
7 Q+
GENERAL DESCRIPTION
The ADRF6820 is a highly integrated demodulator and synthesizer
ideally suited for next generation communication systems. The
feature rich device consists of a high linearity broadband I/Q
demodulator, an integrated fractional-N phase-locked loop (PLL),
and a low phase noise multicore, voltage controlled oscillator
(VCO). The ADRF6820 also integrates a 2:1 RF switch, an on-chip
tunable RF balun, a programmable RF attenuator, and two low
dropout (LDO) regulators. This highly integrated device fits
within a small 6 mm × 6 mm footprint.
The high isolation 2:1 RF switch and on-chip tunable RF balun
enable the ADRF6820 to support two single-ended, 50 Ω
terminated RF inputs. A programmable attenuator ensures
an optimal differential RF input level to the high linearity
demodulator core. The integrated attenuator offers an
attenuation range of 0 dB to 15 dB with a step size of 1 dB.
The ADRF6820 offers two alternatives for generating the
differential local oscillator (LO) input signal: externally via a
high frequency, low phase noise LO signal or internally via the
on-chip fractional-N synthesizer. The integrated synthesizer
enables continuous LO coverage from 356.25 MHz to 2850 MHz.
The PLL reference input can support a wide frequency range
because the divide or multiplication blocks can increase or
decrease the reference frequency to the desired value before it
is passed to the phase frequency detector (PFD).
When selected, the output of the internal fractional-N synthesizer
is applied to a divide-by-2 quadrature phase splitter. From the
external LO path, a 1× LO signal can be applied to the built-in
polyphase filter, or a 2× LO signal can be used with the divide-
by-2 quadrature phase splitter to generate the quadrature LO
inputs to the mixers.
The ADRF6820 is fabricated using an advanced silicon-germanium
BiCMOS process. It is available in a 40-lead, RoHS-compliant,
6 mm × 6 mm LFCSP package with an exposed paddle.
Performance is specified over the −40°C to +85°C temperature
range.
Rev. 0
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rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
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One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
©2013 Analog Devices, Inc. All rights reserved.
Technical Support
www.analog.com
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ADRF6820 Datasheet, Funktion
ADRF6820
Data Sheet
DIGITAL LOGIC SPECIFICATIONS
Table 4.
Parameter
Input Voltage High, VIH
Input Voltage Low, VIL
Output Voltage High, VOH
Output Voltage Low, VOL
Serial Clock Period
Setup Time Between Data and Rising Edge of SCLK
Hold Time Between Data and Rising Edge of SCLK
Setup Time Between Falling Edge of CS and SCLK
Hold Time Between Rising Edge of CS and SCLK
Minimum Period SCLK in a Logic High State
Minimum Period SCLK in a Logic Low State
Maximum Time Delay Between Falling Edge of SCLK and Output Data Valid for
a Read Operation
Maximum Time Delay Between CS Deactivation and SDIO Bus Return to
High Impedance
Test Conditions/Comments
IOH = −100 µA
IOL = 100 µA
tCLK
tDS
tDH
tS
tH
tHIGH
tLOW
tACCESS
tZ
Min Typ Max Unit
1.4 V
0.70 V
2.3 V
0.2 V
38 ns
8 ns
8 ns
10 ns
10 ns
10 ns
10 ns
231 ns
5 ns
Timing Diagram
tDS
tS
tHIGH
tDH
tSCLK
tLOW
tACCESS
CS
SCLK DON'T CARE
SDIO DON'T CARE
A6 A5 A4 A3 A2 A1 A0 R/W D15 D14 D13
Figure 2. Setup and Hold Timing Measurements
tH
D3 D2 D1 D0
DON'T CARE
tZ
DON'T CARE
Rev. 0 | Page 6 of 44
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ADRF6820 pdf, datenblatt
ADRF6820
–60
TA = –40°C
–65 TA = +25°C
TA = +85°C
–70
–75
–80
–85
–90
–95
–100
–105
–110
–115
–120
1.4 1.5 1.6 1.7 1.8 1.9 2.0 2.1 2.2 2.3 2.4 2.5 2.6 2.7 2.8 2.9
LO FREQUENCY (MHz)
Figure 21. 1× PFD Spurs vs. LO Frequency, Measured with
DIV4_EN = 1 (Divide by 2)
–60
TA = –40°C
–65 TA = +25°C
TA = +85°C
–70
–75
–80
–85
–90
–95
–100
–105
–110
–115
–120
1.4 1.5 1.6 1.7 1.8 1.9 2.0 2.1 2.2 2.3 2.4 2.5 2.6 2.7 2.8 2.9
LO FREQUENCY (MHz)
Figure 22. 2× PFD Spurs vs. LO Frequency, Measured with
DIV4_EN = 1 (Divide by 2)
–60
TA = –40°C
–65 TA = +25°C
TA = +85°C
–70
–75
–80
–85
–90
–95
–100
–105
–110
–115
1.4 1.5 1.6 1.7 1.8 1.9 2.0 2.1 2.2 2.3 2.4 2.5 2.6 2.7 2.8 2.9
LO FREQUENCY (GHz)
Figure 23. 3× PFD Spurs vs. LO Frequency, Measured with
DIV4_EN = 1 (Divide by 2)
Data Sheet
400
EXTERNAL LO
INTERNAL LO
350
300
250
200
150
100
50
0
640
TA = –40°C
TA = +25°C
TA = +85°C
1140
1640
2140
2640
LO FREQUENCY (MHz)
Figure 24. VPOS_3P3 Power Supply Current vs. LO Frequency
0
–5
–10
–15
–20 CIN = 0, COUT = 0
CIN = 1, COUT = 1
CIN = 2, COUT = 2
CIN = 3, COUT = 3
–25 CIN = 4, COUT = 4
CIN = 5, COUT = 5
CIN = 6, COUT = 6
CIN = 7, COUT = 7
–30
0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0
FREQUENCY (GHz)
Figure 25. RFIN0/RFIN1 Return Loss for Multiple BAL_CIN and BAL_COUT
Combinations
0
–5
–10
–15
–20
–25
–30
–35
0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0
FREQUENCY (GHz)
Figure 26. Return Loss of Unused RFINx Port vs. Frequency
Rev. 0 | Page 12 of 44
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