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PDF iW-RainboW-G17M-Q7 Data sheet ( Hoja de datos )
| Número de pieza | iW-RainboW-G17M-Q7 | |
| Descripción | ARM Cortex A9 Dual core CPU integrated | |
| Fabricantes | iWave | |
| Logotipo |  |
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Hay una vista previa y un enlace de descarga de iW-RainboW-G17M-Q7 (archivo pdf) en la parte inferior de esta página. Total 2 Páginas | ||
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System On Module RainboW-G17M-Q7
Cyclone V SoC Qseven Module
iW-RainboW-G17M-Q7
HIGHLIGHTS
SPECIFICATIONS
CPU:
Qseven PCB Edge Connector Interfaces:
Altera’s Cyclone V SX SoC FPGA
• Integrated Dual core ARM Cortex-A9
Hard Processor System(HPS)
From HPS:
Gigabit Ethernet - 1 Port (On-SOM PHY)
USB 2.0 Host - 4 Ports (On-SOM HUB)
• FPGA with upto 110K LEs
Memory:
CAN - 1 Port
SD/MMC (8 bit) #
WDOG - 1 Port
16MB QSPI Flash
On-SOM Micro SD Connector #
I2C - 2 Ports
SPI - 1 Port
256MB DDR3 for FPGA
Debug UART - 1 Port
EPCQ Flash* / QSPI Flash for FPGA
2nd UART - 1 Port
Other Control IOs - Through HPS
On Board Peripherals Support:
JTAG Header for FPGA*
From FPGA+:
LVDS LCD - 2 Ports (FPGA Soft IP)/ 23 SE IOs
AC97/I2S Audio (FPGA Soft IP)/ 5 SE IOs
PWM
FPGA IOs - 8 SE IOs
80 Pin Expansion Connector:
From FPGA High Speed Transceivers+:
FPGA IOs (Up to 45 Single Ended IOs - SE IOs): PCIe Gen1 x 4 Lane
9 TX LVDS Pairs / 18 SE IOs
SATA (FPGA Soft IP)
11 RX LVDS Pairs / 22 SE IOs
Form Factor:
5 Single Ended IOs
70mm x 70mm Qseven Specification 2.0
FPGA Dedicated Clock IOs:
Power Input:
General Purpose Clock Inputs (2 LVDS/2 SE) 5V DC
General Purpose Clock Outputs (1 LVDS/2 SE) Operating Temperature:
Others:
-40oC to +85oC Industrial
SMBUS / 2 SE IOs
Operating System:
FPGA JTAG
WEC7, Linux
* Optional
# On-SOM Micro SD Connector and Qseven Edge SD/MMC are sharing the same interface
+ If the FPGA interfaces available in the Qseven edge are not used for Qseven compliance requirement, same interface
pins can be used for custom Industrial/networking interface requirements.
www.iwavesystems.com
Free Datasheet http://www.datasheet4u.com/
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