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PDF APA3160 Data sheet ( Hoja de datos )
| Número de pieza | APA3160 | |
| Descripción | 20W Stereo Digital Class-D Audio Power Amplifier | |
| Fabricantes | ANPEC | |
| Logotipo |  |
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APA3160
20W Stereo Digital Class-D Audio Power Amplifier with EQ and DRC
Features
General Description
• Operating Voltage: 8.0V~24V for PVDD
The APA3160 is a digital input, stereo, high efficiency,
– 3.0V~3.6V for DVDD and AVDD
• High Efficiency Class-D Operation Eliminate the
Class-D audio amplifier available in a TQFP7x7-48P
package.
Need of Heatsinks
The APA3160 accepts the digital serial audio data and
• Digital Serial Audio Input (Stereo Output)
using the digital audio processor to convert the audio
• I2C Control Interface
data becomes the stereo Class-D output speaker
• Sampling Rate can Support from 32kHz to 192kHz amplifier. This provides the seamless integration between
• Separated Volume Control from 24dB to Mute
the codec and the speaker amplifier.
• Soft Mute (50% Duty Cycle)
The APA3160 is a slave device receiving clocks from ex-
• Programmable Dynamic Range Compression
ternal source, and the Class-D’s PWM switching fre-
– Power Limiter
quency is 352.8kHz for the sampling rate 44.1kHz or 384
– Speaker Protection
kHz for sampling 48kHz, depend on the input signal’s
– Night-Mode Listening
sampling rate.
• Programmable Biquads for Speaker EQ
• Shutdown and Mute Function
Pin Configuration
• Thermal and Over-Current Protections with Auto-
Recovery
• Space Saving Package TQFP7x7-48P
• Lead Free and Green Devices Available
(RoHS Compliant)
Applications
• LCD TV
Simplified Application Circuit
OUT_A 1
PVDD_A 2
PVDD_A 3
ABS 4
GDREG 5
NC 6
TM1 7
TM2 8
AVSS 9
PLL_LF 10
AVSS 11
2V5_AV 12
Digital Audio
Source
I2C
Control
MCLK
LRCLK
SCLK
SDIN
OUT_A
OUT_B
APA3160
OUT_C
SDA
SCL
OUT_D
Left
Channel
Speaker
Right
Channel
Speaker
APA3160
TQFP7x7-48P
(TOP VIEW)
36 OUT_D
35 PVDD_D
34 PVDD_D
33 DBS
32 GDREG
31 DVREG
30 AGND
29 GND
28 DVSS
27 DVDD
26 TP3
25 RST
ANPEC reserves the right to make changes to improve reliability or manufacturability without notice, and
advise customers to obtain the latest version of relevant information to verify before placing orders.
Copyright © ANPEC Electronics Corp.
Rev. A.4 - Jan., 2013
1
www.anpec.com.tw
Free Datasheet http://www.datasheet4u.com/
1 page  
APA3160
Serial Audio Ports Slave Mode
Over recommended operating conditions (unless otherwise noted)
Symbol
Parameter
tSetup2
tHold
t(edge)
tr/tf
(SCLK/LRCLK)
Setup Time, SDIN to SCLK
Rising Edge
Hold Time, SDIN to SCLK Rising
Edge
LRCLK Frequency
LRCLK Duty Cycle
SCLK Duty Cycle
SCLK Rising Edges Between
LRCLK Riding Edges
LRCLK Clock Edge With Respect
To The Falling Edge of SCLK
Rise/Fall Time for SCLK/LRCLK
Test Conditions
APA3160
Min.
Typ.
Max.
10 -
-
10 -
-
8K 48K 48K
40 50 60
40 50 60
32 - 64
-1/4 -
1/4
- -8
Unit
ns
kHz
%
SCLK
edges
SCLK
period
ns
Reset Timing
Control signal parameters over recommended operating conditions (unless otherwise noted). Please refer to “Rec-
ommended Use Model” section on usage of all terminals.
Symbol
Parameter
tp(RST)
td(12C_Ready)
Pulse Duration, RST Active.
Time to Enable I2C
Test Conditions
No Load
Min.
100
-
APA3160
Typ.
-
-
Max.
-
13.5
Unit
µs
ms
I2C Serial Control Port Operation
Timing characteristics for I2C Interface signals over recommended operating conditions (unless otherwise noted)
Symbol
Parameter
Test Conditions
fSCL
tW(H)
tW(L)
tr
tf
tsetup1
thold1
t(buf)
tsetup2
thold2
tsetup3
CL
Frequency, SCL
Pulse Duration, SCL High
Pulse Duration, SCL Low
Rise Time, SCL and SDA
Fall Time, SCL and SDA
Setup Time, SCL to SDA
Hold Time, SCL to SDA
Bus Free Time Between Stop
and Start Condition
Setup Time, SCL to Start
Condition
Hold Time, Start condition to SCL
Setup Time, SCL to Stop
Condition
Load Capacitance for Each Bus
Line
No Wait States
Min.
-
0.6
1.3
-
-
100
0
APA3160
Typ.
-
-
-
-
-
-
-
Max.
400
-
-
300
300
-
-
1.3 -
-
0.6 -
0.6 -
0.6 -
-
-
-
- - 400
Unit
kHz
µs
ns
µs
pF
Copyright © ANPEC Electronics Corp.
Rev. A.4 - Jan., 2013
5
www.anpec.com.tw
Free Datasheet http://www.datasheet4u.com/
5 Page 
APA3160
Function Description
Clock And PLL
The APA3160 is a slave device and receives signals from MCLK, SCLK, and LRCLK. The digital audio processor
(DAP) provides all sample rates and MCLK rates which defined in the clock control register.
The APA3160 checks to verify that SCLK is a particular value of 32fS, 48fS, or 64fS. The DAP only provides a 1×fS LRCLK.
The timing relationship of these clocks to SDIN is shown in subsequent sections.
Serial Data Interface
Serial data is an input transmitted to SDIN. The PWM outputs are derived from SDIN. Besides, the APA3160 DAP
receives left-justified, right-justified, and I2S serial data formats with 16, 20, or 24 bit.
PWM Section
The APA3160 DAP device is a high power efficiency and high-performance digital audio reproduction. A noise shaper
is used to increase dynamic range and SNR in the audio band. The PWM section receives 24bit PCM data from the
DAP and outputs two BTL PWM audio output channels.
The PWM section has individual channel dc blocking filters that can be enabled and disabled. The low pass filter cutoff
frequency is less than 1Hz. Besides, the PWM section includes individual channel de-emphasis filters for 44.1 and 48
kHz and can be enabled and disabled.
The adjustable maximum modulation limit of PWM section is from 93.8% to 98.4%.
I2C Compatible Serial Control Interface
The APA3160 DAP receives commands from a system controller through an I2C serial control slave interface. The
serial control interface supports both normal-speed 100kHz and high-speed 400kHz operations without waiting
states. As an added feature, even though the MCLK is absent, the interface operates.
For status registers, the serial control interface provides both single-byte and multi-byte read and write operations;
and for the general control registers, they associated with the PWM.
Copyright © ANPEC Electronics Corp.
Rev. A.4 - Jan., 2013
11
www.anpec.com.tw
Free Datasheet http://www.datasheet4u.com/
11 Page | ||
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