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UJA1163 Schematic ( PDF Datasheet ) - NXP Semiconductors

Teilenummer UJA1163
Beschreibung Mini high-speed CAN system basis chip
Hersteller NXP Semiconductors
Logo NXP Semiconductors Logo 




Gesamt 29 Seiten
UJA1163 Datasheet, Funktion
UJA1163
Mini high-speed CAN system basis chip with Standby mode
Rev. 2 — 17 April 2014
Product data sheet
1. General description
The UJA1163 is a mini high-speed CAN System Basis Chip (SBC) containing an
ISO 11898-2/5 compliant HS-CAN transceiver and an integrated 5 V/100 mA supply for a
microcontroller. The UJA1163 can be operated in a very low-current Standby mode with
bus wake-up capability and supports ISO 11898-6 compliant autonomous CAN biasing.
The UJA1163 implements the standard CAN physical layer as defined in the current
ISO11898 standard (-2 and -5). Pending the release of the updated version of ISO11898
including CAN FD, additional timing parameters defining loop delay symmetry are
included. This implementation enables reliable communication in the CAN FD fast phase
at data rates up to 2 Mbit/s.
2. Features and benefits
2.1 General
ISO 11898-2 and ISO 11898-5 compliant high-speed CAN transceiver
Loop delay symmetry timing enables reliable communication at data rates up to
2 Mbit/s in the CAN FD fast phase
Autonomous bus biasing according to ISO 11898-6
Fully integrated 5 V/100 mA low-drop voltage regulator for 5 V microcontroller
supply (V1)
Bus connections are truly floating when power to pin BAT is off
2.2 Designed for automotive applications
8 kV ElectroStatic Discharge (ESD) protection, according to the Human Body Model
(HBM) on the CAN bus pins
6 kV ESD protection, according to IEC 61000-4-2 on the CAN bus pins and on pin
BAT
CAN bus pins short-circuit proof to 58 V
Battery and CAN bus pins protected against automotive transients according to
ISO 7637-3
Very low quiescent current in Standby mode with full wake-up capability
Leadless HVSON14 package (3.0 mm 4.5 mm) with improved Automated Optical
Inspection (AOI) capability and low thermal resistance
Dark green product (halogen free and Restriction of Hazardous Substances (RoHS)
compliant)






UJA1163 Datasheet, Funktion
NXP Semiconductors
UJA1163
Mini high-speed CAN system basis chip with Standby mode
6.1.1.3 Reset mode
Reset mode is the reset execution state of the SBC. This mode ensures that pin RSTN is
pulled down for a defined time to allow the microcontroller to start up in a controlled
manner.
The transceiver is unable to transmit or receive data in Reset mode. V1 and
overtemperature detection are active.
The UJA1163 switches to Reset mode from any mode in response to a reset event.
The UJA1163 exits Reset mode:
and switches to Standby mode if pin RSTN is released HIGH
if the SBC is forced into Off or Overtemp mode
If a V1 undervoltage event forced the transition to Reset mode, the UJA1163 will remain in
Reset mode until the voltage on pin V1 has recovered.
6.1.1.4 Off mode
The UJA1163 switches to Off mode when the battery is first connected or from any mode
when VBAT < Vth(det)poff. Only power-on detection is enabled; all other modules are
inactive. The UJA1163 starts to boot up when the battery voltage rises above the
power-on detection threshold Vth(det)pon (triggering an initialization process) and switches
to Reset mode after tstartup. Pin RXD is driven LOW when the UJA1163 switches from Off
mode to Standby mode, to indicate a power-on event has occurred.
In Off mode, the CAN pins disengage from the bus (zero load; high-ohmic).
6.1.1.5 Overtemp mode
Overtemp mode is provided to prevent the UJA1163 being damaged by excessive
temperatures. The UJA1163 switches immediately to Overtemp mode from any mode
(other than Off mode) when the global chip temperature rises above the overtemperature
protection activation threshold, Tth(act)otp.
In Overtemp mode, the CAN transmitter and receiver are disabled and the CAN pins are
in a high-ohmic state. No wake-up event will be detected, but a pending wake-up will still
be signalled by a LOW level on pin RXD, which will persist after the overtemperature
event has been cleared. V1 is off and pin RSTN is driven LOW after td(uvd)V1.
The UJA1163 exits Overtemp mode:
and switches to Reset mode if the chip temperature falls below the overtemperature
protection release threshold, Tth(rel)otp
if the device is forced to switch to Off mode (VBAT < Vth(det)poff)
UJA1163
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 2 — 17 April 2014
© NXP Semiconductors N.V. 2014. All rights reserved.
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UJA1163 pdf, datenblatt
NXP Semiconductors
UJA1163
Mini high-speed CAN system basis chip with Standby mode
6.7 CAN fail-safe features
6.7.1 TXD dominant timeout
A TXD dominant time-out timer is started when pin TXD is forced LOW while the
transceiver is in CAN Active Mode. If the LOW state on pin TXD persists for longer than
the TXD dominant time-out time (tto(dom)TXD), the transmitter is disabled, releasing the bus
lines to recessive state. This function prevents a hardware and/or software application
failure from driving the bus lines to a permanent dominant state (blocking all network
communications). The TXD dominant time-out timer is reset when pin TXD goes HIGH.
The TXD dominant time-out time also defines the minimum possible bit rate of 15 kbit/s.
6.7.2 Pull-up on TXD pin
Pin TXD has an internal pull-up towards V1 to ensure a safe defined recessive driver state
in case the pin is left floating.
6.7.3 Pull-down on STBN pin
Pin STBN has an internal pull-down (to GND) to ensure the UJA1163 switches to Standby
mode if STBN is left floating.
6.7.4 Loss of power at pin BAT
A loss of power at pin BAT has no influence on the bus lines or on the microcontroller. No
reverse currents will flow from the bus.
UJA1163
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 2 — 17 April 2014
© NXP Semiconductors N.V. 2014. All rights reserved.
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