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UJA1164 Schematic ( PDF Datasheet ) - NXP Semiconductors

Teilenummer UJA1164
Beschreibung Mini high-speed CAN system basis chip
Hersteller NXP Semiconductors
Logo NXP Semiconductors Logo 




Gesamt 30 Seiten
UJA1164 Datasheet, Funktion
UJA1164
Mini high-speed CAN system basis chip with Standby mode &
watchdog
Rev. 2 — 17 April 2014
Product data sheet
1. General description
The UJA1164 is a mini high-speed CAN System Basis Chip (SBC) containing an
ISO 11898-2/5 compliant HS-CAN transceiver and an integrated 5 V/100 mA supply for a
microcontroller. It also features a watchdog and a Serial Peripheral Interface (SPI). The
UJA1164 can be operated in a very low-current Standby mode with bus wake-up
capability and supports ISO 11898-6 compliant autonomous CAN biasing.
The UJA1164 implements the standard CAN physical layer as defined in the current
ISO11898 standard (-2 and -5). Pending the release of the updated version of ISO11898
including CAN FD, additional timing parameters defining loop delay symmetry are
included. This implementation enables reliable communication in the CAN FD fast phase
at data rates up to 2 Mbit/s.
A number of configuration settings are stored in non-volatile memory, allowing the SBC to
be adapted for use in a specific application. This makes it possible to configure the
power-on behavior of the UJA1164 to meet the requirements of different applications.
2. Features and benefits
2.1 General
ISO 11898-2 and ISO 11898-5 compliant high-speed CAN transceiver
Loop delay symmetry timing enables reliable communication at data rates up to
2 Mbit/s in the CAN FD fast phase
Autonomous bus biasing according to ISO 11898-6
Fully integrated 5 V/100 mA low-drop voltage regulator for 5 V microcontroller
supply (V1)
Bus connections are truly floating when power to pin BAT is off
2.2 Designed for automotive applications
8 kV ElectroStatic Discharge (ESD) protection, according to the Human Body Model
(HBM) on the CAN bus pins
6 kV ESD protection, according to IEC 61000-4-2 on the CAN bus pins and on pin
BAT
CAN bus pins short-circuit proof to 58 V
Battery and CAN bus pins protected against automotive transients according to
ISO 7637-3
Very low quiescent current in Standby mode with full wake-up capability






UJA1164 Datasheet, Funktion
NXP Semiconductors
UJA1164
Mini high-speed CAN system basis chip with Standby mode &
watchdog
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Fig 3. UJA1164 system controller state diagram
DDD
6.1.1.3 Reset mode
Reset mode is the reset execution state of the SBC. This mode ensures that pin RSTN is
pulled down for a defined time to allow the microcontroller to start up in a controlled
manner.
The transceiver is unable to transmit or receive data in Reset mode. The SPI is inactive;
the watchdog is disabled; V1 and overtemperature detection are active.
The UJA1164 switches to Reset mode from any mode in response to a reset event (see
Table 5 for a list of reset sources).
The UJA1164 exits Reset mode:
and switches to Standby mode if pin RSTN is released HIGH
and switches to Forced Normal mode if bit FNMC = 1
if the SBC is forced into Off or Overtemp mode
If a V1 undervoltage event forced the transition to Reset mode, the UJA1164 will remain in
Reset mode until the voltage on pin V1 has recovered.
UJA1164
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 2 — 17 April 2014
© NXP Semiconductors N.V. 2014. All rights reserved.
6 of 53

6 Page









UJA1164 pdf, datenblatt
NXP Semiconductors
UJA1164
Mini high-speed CAN system basis chip with Standby mode &
watchdog
6.2.1 Software Development mode
Software Development mode is provided to simplify the software design process. When
Software Development mode is enabled, the watchdog starts up in Autonomous mode
(WMC = 001) and is inactive after a system reset, overriding the default value (see
Table 7). The watchdog is always off in Autonomous mode if Software Development mode
is enabled (SDMC = 1; see Table 10).
Software can be run without a watchdog in Software Development mode. However, it is
possible to activate and deactivate the watchdog for test purposes by selecting Window or
Timeout mode via bits WMC while the SBC is in Standby mode (note that Window mode
will only be activated when the SBC switches to Normal mode). Software Development
mode is activated via bits SDMC in non-volatile memory (see Table 8).
6.2.2 Watchdog behavior in Window mode
The watchdog runs continuously in Window mode. The watchdog will be in Window mode
if WMC = 100 and the UJA1164 is in Normal mode.
In Window mode, the watchdog can only be triggered during the second half of the
watchdog period. If the watchdog overflows, or is triggered in the first half of the watchdog
period (before ttrig(wd)1), a system reset is performed. After the system reset, the reset
source (either ‘watchdog triggered too early’ or ‘watchdog overflow’) can be read via the
reset source status bits (RSS) in the Main Status register (Table 5). If the watchdog is
triggered in the second half of the watchdog period (after ttrig(wd)1 but before ttrig(wd)2), the
watchdog timer is restarted.
6.2.3 Watchdog behavior in Timeout mode
The watchdog runs continuously in Timeout mode. The watchdog will be in Timeout mode
if WMC = 010 and the UJA1164 is in Normal or Standby mode. The watchdog will also be
in Timeout mode if WMC = 100 and the UJA1164 is in Standby mode. If Autonomous
mode is selected (WMC = 001), the watchdog will be in Timeout mode if one of the
conditions for Timeout mode listed in Table 10 has been satisfied.
In Timeout mode, the watchdog timer can be reset at any time by a watchdog trigger. If the
watchdog overflows, a watchdog failure event (WDF) is captured. If a WDF is already
pending when the watchdog overflows, a system reset is performed. In Timeout mode, the
watchdog can be used as a cyclic wake-up source for the microcontroller when the
UJA1164 is in Standby mode.
6.2.4 Watchdog behavior in Autonomous mode
Autonomous mode is selected when WMC = 001. In Autonomous mode, the watchdog is
either off or in Timeout mode, according to the conditions detailed in Table 10.
Table 10. Watchdog status in Autonomous mode
UJA1164 Operating mode Watchdog status
SDMC = 0
Normal
Timeout mode
Standby; RXD HIGH
off
any other mode
off
Standby; RXD LOW
Timeout mode
SDMC = 1
off
off
off
off
UJA1164
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 2 — 17 April 2014
© NXP Semiconductors N.V. 2014. All rights reserved.
12 of 53

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