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PDF 9536XL Data sheet ( Hoja de datos )
| Número de pieza | 9536XL | |
| Descripción | XC9536XL | |
| Fabricantes | Xilinx | |
| Logotipo |  |
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R XC9536XL High Performance
CPLD
DS058 (v1.2) June 25, 2001
Preliminary Product Specification
Features
• 5 ns pin-to-pin logic delays
• System frequency up to 178 MHz
• 36 macrocells with 800 usable gates
• Available in small footprint packages
- 44-pin PLCC (34 user I/O pins)
- 44-pin VQFP (34 user I/O pins)
- 48-pin CSP (36 user I/O pins)
- 64-pin VQFP (36 user I/O pins)
• Optimized for high-performance 3.3V systems
- Low power operation
- 5V tolerant I/O pins accept 5 V, 3.3V, and 2.5V
signals
- 3.3V or 2.5V output capability
- Advanced 0.35 micron feature size CMOS
FastFLASH™ technology
• Advanced system features
- In-system programmable
- Superior pin-locking and routability with
FastCONNECT II™ switch matrix
- Extra wide 54-input Function Blocks
- Up to 90 product-terms per macrocell with
individual product-term allocation
- Local clock inversion with three global and one
product-term clocks
- Individual output enable per output pin
- Input hysteresis on all user and boundary-scan pin
inputs
- Bus-hold circuitry on all user pin inputs
- Full IEEE Standard 1149.1 boundary-scan (JTAG)
• Fast concurrent programming
• Slew rate control on individual outputs
• Enhanced data security features
• Excellent quality and reliability
- Endurance exceeding 10,000 program/erase
cycles
- 20 year data retention
- ESD protection exceeding 2,000V
• Pin-compatible with 5V-core XC9536 device in the
44-pin PLCC package and the 48-pin CSP package
Description
The XC9536XL is a 3.3V CPLD targeted for high-perfor
mance, low-voltage applications in leading-edge communi
cations and computing systems. It is comprised of two
54V18 Function Blocks, providing 800 usable gates with
propagation delays of 5 ns. See Figure 2 for architecture
overview.
Power Estimation
Power dissipation in CPLDs can vary substantially depend
ing on the system frequency, design application and output
loading. To help reduce power dissipation, each macrocell
in a XC9500XL device may be configured for low-power
mode (from the default high-performance mode). In addi
tion, unused product-terms and macrocells are automati
cally deactivated by the software to further conserve power.
For a general estimate of ICC, the following equation may be
used:
ICC (mA) = MCHP(0.5) + MCLP(0.3) + MC(0.0045 mA/MHz) f
Where:
MCHP = Macrocells in high-performance (default) mode
MCLP = Macrocells in low-power mode
MC = Total number of macrocells used
f = Clock frequency (MHz)
This calculation is based on typical operating conditions
using a pattern of 16-bit up/down counters in each Function
Block with no output loading. The actual ICC value varies
with the design application and should be verified during
normal system operation.
Figure 1 shows the above estimation in a graphical form.
60
178 MHz
50
40
30
20
HighLPowerfPoormwearnc1e25 MHz
10
0 50 100 150 200 250
Clock Frequency (MHz)
DS058_01_061101
Figure 1: Typical ICC vs. Frequency for XC9536XL
© 2000 Xilinx, Inc. All rights reserved. All Xilinx trademarks, registered trademarks, patents, and disclaimers are as listed at http://www.xilinx.com/legal.htm.
All other trademarks and registered trademarks are the property of their respective owners. All specifications are subject to change without notice.
DS058 (v1.2) June 25, 2001
Preliminary Product Specification
www.xilinx.com
1-800-255-7778
1
Free Datasheet http://www.datasheet4u.com/
1 page  
R
Internal Timing Parameters
Symbol
Parameter
Buffer Delays
TIN Input buffer delay
TGCK GCK buffer delay
TGSR GSR buffer delay
TGTS GTS buffer delay
TOUT Output buffer delay
TEN Output buffer enable/disable delay
Product Term Control Delays
TPTCK Product term clock delay
TPTSR Product term set/reset delay
TPTTS Product term 3-state delay
Internal Register and Combinatorial Delays
TPDI Combinatorial logic propagation delay
TSUI Register setup time
THI Register hold time
TECSU Register clock enable setup time
TECHO Register clock enable hold time
TCOI Register clock to output valid time
TAOI Register async. S/R to output delay
TRAI Register async. S/R recover before clock
TLOGI Internal logic delay
TLOGILP Internal low power logic delay
Feedback Delays
TF FastCONNECT II feedback delay
Time Adders
TPTA Incremental product term allocator delay
TSLEW Slew-rate limited delay
XC9536XL High Performance CPLD
XC9536XL-5
Min Max
XC9536XL-7
Min Max
XC9536XL-10
Min Max Units
- 1.5 - 2.3 - 3.5 ns
- 1.1 - 1.5 - 1.8 ns
- 2.0 - 3.1 - 4.5 ns
- 4.0 - 5.0 - 7.0 ns
- 2.0 - 2.5 - 3.0 ns
- 0 - 0 - 0 ns
- 1.6 - 2.4 - 2.7 ns
- 1.0 - 1.4 - 1.8 ns
- 5.5 - 7.2 - 7.5 ns
- 0.5 - 1.3 - 1.7 ns
2.3 - 2.6 - 3.0 - ns
1.4 - 2.2 - 3.5 - ns
2.3 - 2.6 - 3.0 - ns
1.4 - 2.2 - 3.5 - ns
- 0.4 - 0.5 - 1.0 ns
- 6.0 - 6.4 - 7.0 ns
5.0
7.5
10.0
ns
- 1.0 - 1.4 - 1.8 ns
- 5.0 - 6.4 - 7.3 ns
- 1.9 - 3.5 - 4.2 ns
- 0.7 - 0.8 - 1.0 ns
- 3.0 - 4.0 - 4.5 ns
DS058 (v1.2) June 25, 2001
Preliminary Product Specification
www.xilinx.com
1-800-255-7778
5
Free Datasheet http://www.datasheet4u.com/
5 Page | ||
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| PDF Descargar | [ Datasheet 9536XL.PDF ] | |
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