|
|
PDF LTC2627 Data sheet ( Hoja de datos )
| Número de pieza | LTC2627 | |
| Descripción | (LTC26x7) 16-/14-/12-Bit Dual Rail-to-Rail DACs | |
| Fabricantes | Linear Technology | |
| Logotipo |  |
|
Hay una vista previa y un enlace de descarga de LTC2627 (archivo pdf) en la parte inferior de esta página. Total 20 Páginas | ||
|
No Preview Available !
LTC2607/LTC2617/LTC2627
16-/14-/12-Bit Dual Rail-to-Rail
DACs with I2C Interface
Features
Description
n Smallest Pin-Compatible Dual DACs:
LTC2607: 16 Bits
LTC2617: 14 Bits
LTC2627: 12 Bits
n Guaranteed Monotonic Over Temperature
n 27 Selectable Addresses
n 400kHz I2C Interface
n Wide 2.7V to 5.5V Supply Range
n Low Power Operation: 260µA per DAC at 3V
n Power Down to 1µA, Max
n High Rail-to-Rail Output Drive (±15mA, Min)
n Ultralow Crosstalk (30µV)
n Double-Buffered Data Latches
n Asynchronous DAC Update Pin
n LTC2607/LTC2617/LTC2627: Power-On Reset to
Zero Scale
n LTC2607-1/LTC2617-1/LTC2627-1: Power-On Reset
to Mid-Scale
n Tiny (3mm × 4mm) 12-Lead DFN Package
Applications
n Mobile Communications
n Process Control and Industrial Automation
n Instrumentation
n Automatic Test Equipment
The LTC®2607/LTC2617/LTC2627 are dual 16-, 14- and
12-bit, 2.7V to 5.5V rail-to-rail voltage output DACs in a
12-lead DFN package. They have built-in high performance
output buffers and are guaranteed monotonic.
These parts establish new board-density benchmarks for
16- and 14-bit DACs and advance performance standards
for output drive and load regulation in single-supply,
voltage-output DACs.
The parts use a 2-wire, I2C compatible serial interface. The
LTC2607/LTC2617/LTC2627 operate in both the standard
mode (clock rate of 100kHz) and the fast mode (clock rate
of 400kHz). An asynchronous DAC update pin (LDAC) is
also included.
The LTC2607/LTC2617/LTC2627 incorporate a power-on
reset circuit. During power-up, the voltage outputs rise less
than 10mV above zero scale; and after power-up, they stay
at zero scale until a valid write and update take place. The
power-on reset circuit resets the LTC2607-1/LTC2617-1/
LTC2627-1 to mid-scale. The voltage outputs stay at mid-
scale until a valid write and update takes place.
L, LT, LTC, LTM, Linear Technology and the Linear logo are registered trademarks of Linear
Technology Corporation. All other trademarks are the property of their respective owners.
Protected by U.S. Patents including 5396245 and 6891433. Patent Pending.
Block Diagram
REFLO 11
GND 10
12
VOUTA
12-/14-/16-BIT DAC
DAC REGISTER
REF 9
VCC 8
12-/14-/16-BIT DAC
7
VOUTB
DAC REGISTER
INPUT REGISTER
INPUT REGISTER
32-BIT SHIFT REGISTER
CA0 1 CA1 2 LDAC 3
2-WIRE INTERFACE
SCL 4
SDA 5
CA2 6
2607 BD01a
Differential Nonlinearity
(LTC2607)
1.0 VCC = 5V
0.8 VREF = 4.096V
0.6
0.4
0.2
0
–0.2
–0.4
–0.6
–0.8
–1.0 0
16384
32768
CODE
49152 65535
2607 BD01b
26071727fa
Free Datasheet http://www.datasheet4u.com/
1 page  
LTC2607/LTC2617/LTC2627
E lectrical Characteristics The l denotes the specifications which apply over the full operating
temperature range, otherwise specifications
VOUT unloaded, unless otherwise noted.
are
at
TA
=
25°C.
REF
=
4.096V
(VCC
=
5V),
REF
=
2.048V
(VCC
=
2.7V),
REFLO
=
0V,
LTC2627/LTC2627-1 LTC2617/LTC2617-1 LTC2607/LTC2607-1
SYMBOL PARAMETER
CONDITIONS
MIN TYP MAX MIN TYP MAX MIN TYP MAX UNITS
AC Performance
tS Settling Time (Note 7)
±0.024% (±1LSB at 12 Bits)
±0.006% (±1LSB at 14 Bits)
±0.0015% (±1LSB at 16 Bits)
7
7 7 µs
9 9 µs
10 µs
Settling Time for 1LSB Step ±0.024% (±1LSB at 12 Bits)
2.7
2.7
2.7 µs
(Note 8)
±0.006% (±1LSB at 14 Bits)
4.8 4.8 µs
±0.0015% (±1LSB at 16 Bits)
5.2 µs
Voltage Output Slew Rate
0.8 0.8 0.8 V/µs
Capacitive Load Driving
1000 1000 1000 pF
Glitch Impulse
At Mid-Scale Transition
12 12 12 nV • s
Multiplying Bandwidth
180 180 180 kHz
en Output Voltage Noise Density At f = 1kHz
At f = 10kHz
120 120 120 nV/√Hz
100 100 100 nV/√Hz
Output Voltage Noise
0.1Hz to 10Hz
15 15 15 µVP-P
Timing Characteristics The l denotes the specifications which apply over the full operating temperature
range, otherwise specifications are at TA = 25°C. (See Figure 1) (Notes 10, 11)
SYMBOL PARAMETER
CONDITIONS
MIN TYP MAX UNITS
VCC = 2.7V to 5.5V
fSCL SCL Clock Frequency
tHD(STA) Hold Time (Repeated) Start Condition
tLOW Low Period of the SCL Clock Pin
tHIGH High Period of the SCL Clock Pin
tSU(STA) Set-Up Time for a Repeated Start Condition
tHD(DAT) Data Hold Time
tSU(DAT) Data Set-Up Time
tr Rise Time of Both SDA and SCL Signals
tf Fall Time of Both SDA and SCL Signals
tSU(STO) Set-Up Time for Stop Condition
tBUF Bus Free Time Between a Stop and Start Condition
t1
Falling Edge of 9th Clock of the 3rd Input Byte to
LDAC High or Low Transition
(Note 9)
(Note 9)
l0
l 0.6
l 1.3
l 0.6
l 0.6
l0
l 100
l 20 + 0.1CB
l 20 + 0.1CB
l 0.6
l 1.3
l 400
400 kHz
µs
µs
µs
µs
0.9 µs
ns
300 ns
300 ns
µs
µs
ns
t2 LDAC Low Pulse Width
l 20
ns
Note 1: Stresses beyond those listed under Absolute Maximum Ratings
may cause permanent damage to the device. Exposure to any Absolute
Maximum Rating condition for extended periods may affect device
reliability and lifetime.
Note
2N –
2:
1,
wLihneeraerNityisanthdemreosnoolutotnioincitayndarkeLdiesfignievdenfrboymkLco=d0e.0k1L6to(2cNo/dVeREF),
rounded to the nearest whole code. For VREF = 4.096V and N = 16, kL =
256 and linearity is defined from code 256 to code 65,535.
Note 3: SDA, SCL and LDAC at 0V or VCC, CA0, CA1 and CA2 Floating.
Note 4: DC crosstalk is measured with VCC = 5V and VREF = 4.096V, with
the measured DAC at mid-scale, unless otherwise noted.
Note 5: RL = 2kΩ to GND or VCC.
Note 6: Inferred from measurement at code kL (Note 2) and at full scale.
Note 7: VCC = 5V, VREF = 4.096V. DAC is stepped 1/4 scale to 3/4 scale
and 3/4 scale to 1/4 scale. Load is 2k in parallel with 200pF to GND.
Note 8: VCC = 5V, VREF = 4.096V. DAC is stepped ±1LSB between half
scale and half scale – 1. Load is 2k in parallel with 200pF to GND.
Note 9: CB = capacitance of one bus line in pF.
Note 10: All values refer to VIH(MIN) and VIL(MAX) levels.
Note 11: These specifications apply to LTC2607/LTC2607-1,
LTC2617/LTC2617-1, LTC2627/LTC2627-1.
Note 12: Guaranteed by design and not production tested.
26071727fa
Free Datasheet http://www.datasheet4u.com/
5 Page 
Block Diagram
REFLO 11
GND 10
12
VOUTA
12-/14-/16-BIT DAC
DAC REGISTER
LTC2607/LTC2617/LTC2627
REF 9
VCC 8
12-/14-/16-BIT DAC
7
VOUTB
DAC REGISTER
INPUT REGISTER
INPUT REGISTER
32-BIT SHIFT REGISTER
CA0 1 CA1 2 LDAC 3
2-WIRE INTERFACE
SCL 4
SDA 5
CA2 6
2607 BD
Test Circuits
Test Circuit 1
Test Circuit 2
VDD
100Ω
VIH(CAn)/VIL(CAn)
CAn
RINH/RINL/RINF
CAn
GND
2607 TC
26071727fa
11
Free Datasheet http://www.datasheet4u.com/
11 Page | ||
| Páginas | Total 20 Páginas | |
| PDF Descargar | [ Datasheet LTC2627.PDF ] | |
Hoja de datos destacado
| Número de pieza | Descripción | Fabricantes |
| LTC2620 | (LTC2600 - LTC2620) 3V/5V Octal 12-bit Rail-to-rail DAC | Linear Technology |
| LTC2621 | (LTC2601 - LTC2621) 12-Bit Rail-to-rail DACs | Linear Technology |
| LTC2622 | (LTC2602 - LTC2622) Rail-to-rail DACs | Linear Technology |
| LTC2624 | (LTC2604 - LTC2624) Rail-to-rail Voltage Output DACs | Linear Technology |
| Número de pieza | Descripción | Fabricantes |
| SLA6805M | High Voltage 3 phase Motor Driver IC. |
 Sanken |
| SDC1742 | 12- and 14-Bit Hybrid Synchro / Resolver-to-Digital Converters. |
 Analog Devices |
|
DataSheet.es es una pagina web que funciona como un repositorio de manuales o hoja de datos de muchos de los productos más populares, |
| DataSheet.es | 2020 | Privacy Policy | Contacto | Buscar |