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74LVC125A Schematic ( PDF Datasheet ) - NXP Semiconductors

Teilenummer 74LVC125A
Beschreibung Quad buffer/line driver
Hersteller NXP Semiconductors
Logo NXP Semiconductors Logo 




Gesamt 16 Seiten
74LVC125A Datasheet, Funktion
74LVC125A
Quad buffer/line driver with 5 V tolerant input/outputs; 3-state
Rev. 7 — 11 April 2013
Product data sheet
1. General description
The 74LVC125A consists of four non-inverting buffers/line drivers with 3-state outputs
(nY) that are controlled by the output enable input (nOE). A HIGH at nOE causes the
outputs to assume a high-impedance OFF-state.
Inputs can be driven from either 3.3 V or 5 V devices. When disabled, up to 5.5 V can be
applied to the outputs.
2. Features and benefits
5 V tolerant inputs/outputs for interfacing with 5 V logic
Wide supply voltage range from 1.2 V to 3.6 V
CMOS low power consumption
Direct interface with TTL levels
Complies with JEDEC standard:
JESD8-7A (1.65 V to 1.95 V)
JESD8-5A (2.3 V to 2.7 V)
JESD8-C/JESD36 (2.7 V to 3.6 V)
ESD protection:
HBM JESD22-A114F exceeds 2000 V
MM JESD22-A115-B exceeds 200 V
CDM JESD22-C101E exceeds 1000 V
Multiple package options
Specified from 40 C to +85 C and 40 C to +125 C
Free Datasheet http://www.datasheet4u.com/






74LVC125A Datasheet, Funktion
NXP Semiconductors
74LVC125A
Quad buffer/line driver with 5 V tolerant input/outputs; 3-state
10. Dynamic characteristics
Table 7. Dynamic characteristics
Voltages are referenced to GND (ground = 0 V). For test circuit see Figure 8.
Symbol Parameter
Conditions
40 C to +85 C
Min Typ[1] Max
tpd propagation delay nA to nY; see Figure 6
[2]
VCC = 1.2 V
- 12.0 -
VCC = 1.65 V to 1.95 V
1.5 5.4 11.0
VCC = 2.3 V to 2.7 V
1.0 2.9 5.7
VCC = 2.7 V
1.5 2.8 5.5
ten enable time
VCC = 3.0 V to 3.6 V
nOE to nY; see Figure 7
1.0 2.5 4.8
[2]
VCC = 1.2 V
- 16.0 -
VCC = 1.65 V to 1.95 V
1.0 5.0 12.2
VCC = 2.3 V to 2.7 V
0.5 2.9 6.8
VCC = 2.7 V
1.5 3.1 6.6
tdis disable time
VCC = 3.0 V to 3.6 V
nOE to nY; see Figure 7
1.0 2.3 5.4
[2]
VCC = 1.2 V
- 7.0 -
VCC = 1.65 V to 1.95 V
2.2 4.6 7.5
VCC = 2.3 V to 2.7 V
0.5 2.6 4.2
VCC = 2.7 V
1.5 3.1 5.0
tsk(o)
CPD
output skew time
power dissipation
capacitance
VCC = 3.0 V to 3.6 V
VCC = 3.0 V to 3.6 V
per buffer; VI = GND to VCC
VCC = 1.65 V to 1.95 V
1.0 3.2 4.6
[3] -
- 1.0
[4]
- 6.0 -
VCC = 2.3 V to 2.7 V
- 9.4 -
VCC = 3.0 V to 3.6 V
- 12.4 -
40 C to +125 C Unit
Min Max
- - ns
1.5 12.8 ns
1.0 6.7 ns
1.5 7.0 ns
1.0 6.0 ns
- - ns
1.0 14.2 ns
0.5 7.9 ns
1.5 8.5 ns
1.0 7.0 ns
- - ns
2.2 8.7 ns
0.5 5.0 ns
1.5 6.5 ns
1.0 6.0 ns
- 1.5 ns
- - pF
- - pF
- - pF
[1] Typical values are measured at Tamb = 25 C and VCC = 1.2 V, 1.8 V, 2.5 V, 2.7 V, and 3.3 V respectively.
[2] tpd is the same as tPLH and tPHL.
ten is the same as tPZL and tPZH.
tdis is the same as tPLZ and tPHZ.
[3] Skew between any two outputs of the same package switching in the same direction. This parameter is guaranteed by design.
[4] CPD is used to determine the dynamic power dissipation (PD in W).
PD = CPD VCC2 fi N + (CL VCC2 fo) where:
fi = input frequency in MHz; fo = output frequency in MHz
CL = output load capacitance in pF
VCC = supply voltage in Volts
N = number of inputs switching
(CL VCC2 fo) = sum of the outputs.
74LVC125A
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 7 — 11 April 2013
© NXP B.V. 2013. All rights reserved.
6 of 16
Free Datasheet http://www.datasheet4u.com/

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74LVC125A pdf, datenblatt
NXP Semiconductors
74LVC125A
Quad buffer/line driver with 5 V tolerant input/outputs; 3-state
DHVQFN14: plastic dual in-line compatible thermal enhanced very thin quad flat package; no leads;
14 terminals; body 2.5 x 3 x 0.85 mm
SOT762-1
D BA
terminal 1
index area
A
A1
E
c
detail X
terminal 1
index area
L
e
2
1
Eh
14
e1
b
6
vM C AB
wM C
7
e
8
y1 C
C
y
13 9
Dh
0 2.5
5 mm
X
scale
DIMENSIONS (mm are the original dimensions)
UNIT
A(1)
max.
A1
b
c D(1) Dh E(1) Eh e e1 L
v
w
y
y1
mm
1
0.05
0.00
0.30
0.18
0.2
3.1
2.9
1.65
1.35
2.6
2.4
1.15
0.85
0.5
2
0.5
0.3
0.1 0.05 0.05
0.1
Note
1. Plastic or metal protrusions of 0.075 mm maximum per side are not included.
OUTLINE
VERSION
IEC
REFERENCES
JEDEC
JEITA
EUROPEAN
PROJECTION
SOT762-1
---
MO-241
---
ISSUE DATE
02-10-17
03-01-27
Fig 12. Package outline SOT762-1 (DHVQFN14)
74LVC125A
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 7 — 11 April 2013
© NXP B.V. 2013. All rights reserved.
12 of 16
Free Datasheet http://www.datasheet4u.com/

12 Page





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