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TW9903 Schematic ( PDF Datasheet ) - Techwell

Teilenummer TW9903
Beschreibung Multi-standard Video Decoder
Hersteller Techwell
Logo Techwell Logo 




Gesamt 30 Seiten
TW9903 Datasheet, Funktion
Techwell, Inc.
TW9903 – Multi-standard Video
Decoder With High Quality Down Scaler
Preliminary Data Sheet
Techwell Confidential. Information may change
without notice.
Disclaimer
This document provides technical information for the user. Techwell, Inc. reserves the right to modify the
information in this document as necessary. The customer should make sure that they have the most
recent data sheet version. Techwell, Inc. holds no responsibility for any errors that may appear in this
document. Customers should take appropriate action to ensure their use of the products does not infringe
upon any patents. Techwell, Inc. respects valid patent rights of third parties and does not infringe upon or
assist others to infringe upon such rights.
TECHWELL, INC.
1
REV. 0.92 ( B )
06/02/2002
Free Datasheet http://www.datasheet4u.com/






TW9903 Datasheet, Funktion
TW9903
Software selectable analog inputs allow several possible input combinations:
1. Up to four composite video inputs. 2. Three composite, one S-video.
The input video signals in any certain channel maybe momentarily connected together through the
equivalent of a 200 ohm resistor during multiplexer switching. Therefore, the multiplexer cannot be
used for switching on a real-time pixel-by-pixel basis.
Clamping and Automatic Gain Control
All three analog channels have built-in clamping circuit that restore the signal DC level. The Y
channel restores the back porch of the digitized video to a level of 64 or a programmable level. The
C_Pb channel restores the back porch of the digitized video to a level of 128. This operation is
automatic through internal feedback loop.
The Automatic Gain Control (AGC) of the Y channel adjusts input gain so that the sync tip is at a
desired level. A programmable white peak protection logic is included to prevent saturation in the
case of abnormal proportion between sync and white peak level.
Analog to Digital Converter
TW9903 contains three 8-bit pipelined ADCs that consume less power than conventional flash
ADC. The output of the Clamp and AGC connects to one ADC that digitizes the composite input or
the Y signal of the S-Video input. The second ADC digitizes the C signal when decoding S-video
signal.
Sync Processing
The sync processor of TW9903 detects horizontal synchronization and vertical synchronization
signals in the composite video or in the Y signal of an S-video or component signal. The processor
contains a digital phase-locked-loop and decision logic to achieve reliable sync detection in stable
signal as well as in unstable signals such as those from VCR fast forward or backward.
Horizontal sync processing
The horizontal synchronization processing contains a sync separator, a phase-locked-loop (PLL),
and the related decision logic.
The horizontal sync detector detects the presence of a horizontal sync tip by examining low-pass
filtered input samples whose level is lower than a threshold. After sufficient low levels are detected,
a horizontal sync is recognized. Additional logic is also used to avoid false detection on glitches.
The horizontal PLL locks onto the extracted horizontal sync in all conditions to provide jitter free
image output. From there, the PLL also provides orthogonal sampling raster for the down stream
processor. The PLL has free running frequency that matches the standard raster frequency. It also
has wide lock-in range for tracking any non-standard video signal.
In case the horizontal sync is missing, a “free-wheel” mechanism keeps generating horizontal sync
signal until horizontal sync is detected again. This option can also be turned off for some
applications that determine video loss by detecting the existence of horizontal sync.
TECHWELL, INC.
6
REV. 0.92 ( B )
06/02/2002
Free Datasheet http://www.datasheet4u.com/

6 Page









TW9903 pdf, datenblatt
TW9903
Pin Name VD15 VD14 VD13 VD12 VD11 VD10 VD9 VD8 VD7 VD6 VD5 VD4 VD3 VD2 VD1 VD0
CK1 2N Y7 Y6 Y5 Y4 Y3 Y2 Y1 Y0 Cb7 Cb6 Cb5 Cb4 Cb3 Cb2 Cb1 Cb0
2N+1 Y7 Y6 Y5 Y4 Y3 Y2 Y1 Y0 Cr7 Cr6 Cr5 Cr4 Cr3 Cr2 Cr1 Cr0
CK2 4N Cb7 Cb6 Cb5 Cb4 Cb3 Cb2 Cb1 Cb0
4N+1 Y7 Y6 Y5 Y4 Y3 Y2 Y1 Y0
4N+2 Cr7 Cr6 Cr5 Cr4 Cr3 Cr2 Cr1 Cr0
4N+3 Y7 Y6 Y5 Y4 Y3 Y2 Y1 Y0
ITU-R SAV and EAV sequence, YCbCr data and blanking
BT.656
data are transferred on these pins
Table 2. Output mapping between various data formats
CLKX2
CLKX1
VD[15:8]
Cb0 Y0 Cr0 Y1 Cb2 Y2 Cr2 Y3 Cb4 Y4 Cr4 Y5 Cb6 Y6 Cr6
Figure 3a. 8-bit Video Data Output timing
CLKX2
CLKX1
VD[15:8]
VD[7:0]
Y0 Y1 Y2 Y3 Y4 Y5
Cb0 Cr0 Cb2 Cr2 Cb4 Cr4
Y6
Cb6
Figure 3b. 16-bit Video Data Output Timing
Clock and Control Signal Output
The default output format of TW9903 is a synchronous 8-bit YCbCr 4:2:2 data format with separate
syncs and flags. Video data is compliant with ITU-601format. HSYNC, VSYNC, HACTIVE,
VACTIVE, LVALID (MPOUT), FIELD have the same output timings in both 8-bit output mode and
16-bit output modes. All control signals are synchronous with the rising edge of CLKX2.and they
are illustrated with default polarity register setting values bellow.
TECHWELL, INC.
12
REV. 0.92 ( B )
06/02/2002
Free Datasheet http://www.d

12 Page





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