PDF ADF4159 Data sheet ( Hoja de datos )

Número de pieza	ADF4159
Descripción	Fractional-N Frequency Synthesizer
Fabricantes	Analog Devices
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No Preview Available ! Data Sheet Direct Modulation/Fast Waveform Generating, 13 GHz, Fractional-N Frequency Synthesizer ADF4159 FEATURES GENERAL DESCRIPTION RF bandwidth to 13 GHz High and low speed FMCW ramp generation 25-bit fixed modulus allows subhertz frequency resolution PFD frequencies up to 110 MHz Normalized phase noise floor of −224 dBc/Hz FSK and PSK functions Sawtooth, triangular, and parabolic waveform generation Ramp superimposed with FSK Ramp with 2 different sweep rates Ramp delay, frequency readback, and interrupt functions Programmable phase control 2.7 V to 3.45 V analog power supply 1.8 V digital power supply Programmable charge pump currents 3-wire serial interface Digital lock detect ESD performance: 3000 V HBM, 1000 V CDM The ADF4159 is a 13 GHz, fractional-N frequency synthesizer with modulation and both fast and slow waveform generation capability. The part uses a 25-bit fixed modulus, allowing subhertz frequency resolution. The ADF4159 consists of a low noise digital phase frequency detector (PFD), a precision charge pump, and a programmable reference divider. The Σ-Δ-based fractional interpolator allows programmable fractional-N division. The INT and FRAC registers define an overall N divider as N = INT + (FRAC/225). The ADF4159 can be used to implement frequency shift keying (FSK) and phase shift keying (PSK) modulation. Frequency sweep modes are also available to generate various waveforms in the frequency domain, for example, sawtooth and triangular wave- forms. The ADF4159 features cycle slip reduction circuitry, which enables faster lock times without the need for modifications to the loop filter. APPLICATIONS FMCW radars Communications test equipment Communications infrastructure Control of all on-chip registers is via a simple 3-wire interface. The ADF4159 operates with an analog power supply in the range of 2.7 V to 3.45 V and a digital power supply in the range of 1.62 V to 1.98 V. The device can be powered down when not in use. FUNCTIONAL BLOCK DIAGRAM AVDD DVDD SDVDD VP RSET ADF4159 REFIN ×2 DOUBLER 5-BIT R COUNTER ÷2 DIVIDER HIGH-Z MUXOUT OUTPUT MUX CE TXDATA DGND SDOUT DVDD RDIV NDIV LOCK DETECT THIRD-ORDER FRACTIONAL INTERPOLATOR + PHASE FREQUENCY DETECTOR – REFERENCE SW2 CHARGE PUMP CSR FAST LOCK SWITCH CP SW1 N COUNTER + – RFINA RFINB CLK DATA LE 32-BIT DATA REGISTER FRACTION VALUE MODULUS 225 VALUE INTEGER VALUE AGND DGND SDGND Figure 1. CPGND Rev. B Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibilityisassumedbyAnalogDevices for itsuse,nor foranyinfringementsofpatentsor other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarksandregisteredtrademarksarethepropertyoftheirrespectiveowners. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 ©2013 Analog Devices, Inc. All rights reserved. Technical Support www.analog.com Free Datasheet http://www.datasheet4u.com/ 1 page Data Sheet ADF4159 Table 3. Read Timing Parameter Limit at TMIN to TMAX t11 tPFD + 20 t2 20 t3 25 t4 25 t5 10 Unit ns min ns min ns min ns min ns min Description TXDATA setup time CLK setup time to data (on MUXOUT) CLK high duration CLK low duration CLK to LE setup time 1 tPFD is the period of the PFD frequency; for example, if the PFD frequency is 50 MHz, tPFD = 20 ns. Read Timing Diagram TXDATA CLK t1 t3 t4 MUXOUT DB36 t2 DB35 DB2 DB1 LE NOTES 1. LE SHOULD BE KEPT HIGH DURING READBACK. Figure 3. Read Timing Diagram DB0 t5 500µA IOL TO MUXOUT PIN CL 10pF 0.9V 100µA IOH Figure 4. Load Circuit for MUXOUT Timing, CL = 10 pF Rev. B \| Page 5 of 36 Free Datasheet http://www.datasheet4u.com/ 5 Page Data Sheet PHASE FREQUENCY DETECTOR (PFD) AND CHARGE PUMP The PFD takes inputs from the R counter and N counter and produces an output proportional to the phase and frequency difference between them. Figure 21 shows a simplified sche- matic of the PFD. HIGH UP D1 Q1 U1 +IN CLR1 DELAY U3 CHARGE PUMP CP HIGH CLR2 DOWN D2 Q2 U2 –IN Figure 21. PFD Simplified Schematic The PFD includes a fixed delay element that sets the width of the antibacklash pulse, which is typically 1 ns. This pulse ensures that there is no dead zone in the PFD transfer function and gives a consistent reference spur level. MUXOUT AND LOCK DETECT The multiplexer output on the ADF4159 allows the user to access various internal points on the chip. The state of MUXOUT is controlled by the M4, M3, M2, and M1 bits in Register R0 (see Figure 25). Figure 22 shows the MUXOUT section in block diagram form. THREE-S TATE OUTPUT DVDD DGND R DIVIDER OUTPUT N DIVIDER OUTPUT DIGITAL LOCK DETECT MUX CONTROL SERIAL DATA OUTPUT CLK DIVIDER OUTPUT R DIVIDER/2 N DIVIDER/2 READBACK TO MUXOUT Figure 22. MUXOUT Schematic DVDD MUXOUT DGND ADF4159 INPUT SHIFT REGISTER The ADF4159 digital section includes a 5-bit R counter, a 12-bit INT counter, and a 25-bit FRAC counter. Data is clocked into the 32-bit input shift register on each rising edge of CLK. The data is clocked in MSB first. Data is transferred from the input shift register to one of eight latches on the rising edge of LE. The destination latch is determined by the state of the three control bits (C3, C2, and C1) in the input shift register. As shown in Figure 2, the control bits are the three LSBs (DB2, DB1, and DB0, respectively). Table 7 shows the truth table for these bits. Figure 23 and Figure 24 provide a summary of how the latches are programmed. Table 7. Truth Table for the C3, C2, and C1 Control Bits Control Bits C3 C2 C1 Register 0 0 0 R0 0 0 1 R1 0 1 0 R2 0 1 1 R3 1 0 0 R4 1 0 1 R5 1 1 0 R6 1 1 1 R7 PROGRAM MODES Table 7 and Figure 25 through Figure 32 show how the program modes are set up in the ADF4159. The following settings in the ADF4159 are double buffered: LSB fractional value, phase value, charge pump current setting, reference divide-by-2, reference doubler, R counter value, and CLK1 divider value. Before the part uses a new value for any double-buffered setting, the following two events must occur: 1. The new value is latched into the device by writing to the appropriate register. 2. A new write is performed to Register 0 (R0). For example, updating the fractional value involves a write to the 13 LSB bits in R1 and the 12 MSB bits in R0. R1 must be written to first, followed by the write to R0. The frequency change begins after the write to R0. Double-buffering ensures that the bits written to R1 do not take effect until after the write to R0. Rev. B \| Page 11 of 36 Free Datasheet http://www.datasheet4u.com/ 11 Page

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