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PDF ADF4157 Data sheet ( Hoja de datos )
| Número de pieza | ADF4157 | |
| Descripción | High Resolution 6 GHz Fractional-N Frequency Synthesizer | |
| Fabricantes | Analog Devices | |
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Data Sheet
High Resolution 6 GHz Fractional-N
Frequency Synthesizer
ADF4157
FEATURES
GENERAL DESCRIPTION
RF bandwidth to 6 GHz
25-bit fixed modulus allows subhertz frequency resolution
2.7 V to 3.3 V power supply
Separate VP allows extended tuning voltage
Programmable charge pump currents
3-wire serial interface
Digital lock detect
Power-down mode
Pin compatible with the following frequency synthesizers:
ADF4110/ADF4111/ADF4112/ADF4113/
ADF4106/ADF4153/ADF4154/ADF4156
Cycle slip reduction for faster lock times
APPLICATIONS
The ADF4157 is a 6 GHz fractional-N frequency synthesizer with
a 25-bit fixed modulus, allowing subhertz frequency resolution
at 6 GHz. It consists of a low noise digital phase frequency detector
(PFD), a precision charge pump, and a programmable reference
divider. There is a Σ-Δ based fractional interpolator to allow
programmable fractional-N division. The INT and FRAC values
define an overall N divider, N = INT + (FRAC/225). The ADF4157
features cycle slip reduction circuitry, which leads to faster lock
times without the need for modifications to the loop filter.
Control of all on-chip registers is via a simple 3-wire interface.
The device operates with a power supply ranging from 2.7 V to
3.3 V and can be powered down when not in use.
Satellite communications terminals, radar equipment
Instrumentation equipment
Personal mobile radio (PMR)
Base stations for mobile radio
Wireless handsets
FUNCTIONAL BLOCK DIAGRAM
AVDD DVDD VP
RSET
ADF4157
REFIN
MUXOUT
CE
×2
DOUBLER
5-BIT
R COUNTER
÷2
DIVIDER
HIGH Z
OUTPUT
MUX
VDD
DGND
SDOUT
VDD
RDIV
NDIV
LOCK
DETECT
THIRD-ORDER
FRACTIONAL
INTERPOLATOR
REFERENCE
+ PHASE
FREQUENCY
DETECTOR
–
CHARGE
PUMP
CURRENT
SETTING
CSR
CP
RFCP4 RFCP3 RFCP2 RFCP1
N COUNTER
RFINA
RFINB
CLK
DATA
LE
32-BIT
DATA
REGISTER
FRACTION MODULUS
REG
225
INTEGER
REG
AGND
DGND
Figure 1.
CPGND
Rev. D
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibilityisassumedbyAnalogDevices for itsuse,nor foranyinfringementsofpatentsor other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarksandregisteredtrademarksarethepropertyoftheirrespectiveowners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
www.analog.com
Fax: 781.461.3113 ©2007–2012 Analog Devices, Inc. All rights reserved.
1 page  
ADF4157
Data Sheet
TIMING SPECIFICATIONS
AVDD = DVDD = 2.7 V to 3.3 V; VP = AVDD to 5.5 V; AGND = DGND = 0 V; TA = TMIN to TMAX, unless otherwise noted;
dBm referred to 50 Ω.
Table 2.
Parameter
t1
t2
t3
t4
t5
t6
t7
Limit at TMIN to TMAX (B Version)
20
10
10
25
25
10
20
Unit
ns min
ns min
ns min
ns min
ns min
ns min
ns min
Test Conditions/Comments
LE setup time
Data to clock setup time
Data to clock hold time
Clock high duration
Clock low duration
Clock to LE setup time
LE pulse width
CLK
DATA
DB23 (MSB)
LE
t1
LE
t4 t5
t2 t3
DB22
DB2
(CONTROL BIT C3)
DB1
(CONTROL BIT C2)
Figure 2. Timing Diagram
DB0 (LSB)
(CONTROL BIT C1)
t7
t6
Rev. D | Page 4 of 24
5 Page 
ADF4157
PHASE FREQUENCY DETECTOR (PFD) AND
CHARGE PUMP
The PFD takes inputs from the R counter and the N counter
and produces an output proportional to the phase and fre-
quency difference between them. Figure 14 is a simplified
schematic of the phase frequency detector. The PFD includes
a fixed delay element that sets the width of the antibacklash
pulse, which is typically 3 ns. This pulse ensures that there is no
dead zone in the PFD transfer function and gives a consistent
reference spur level.
UP
HI D1 Q1
U1
+IN CLR1
DELAY
U3
CHARGE
PUMP
CP
CLR2 DOWN
HI D2 Q2
U2
–IN
Figure 14. PFD Simplified Schematic
MUXOUT AND LOCK DETECT
The output multiplexer on the ADF4157 allows the user to access
various internal points on the chip. The state of MUXOUT is
controlled by M4, M3, M2, and M1 (see Figure 17). Figure 15
shows the MUXOUT section in block diagram form.
THREE-STATE OUTPUT
DVDD
DGND
R DIVIDER OUTPUT
N DIVIDER OUTPUT
ANALOG LOCK DETECT
DIGITAL LOCK DETECT
MUX
CONTROL
SERIAL DATA OUTPUT
CLK DIVIDER OUTPUT
FASTLOCK SWITCH
R DIVIDER/2
N DIVIDER/2
Figure 15. MUXOUT Schematic
DVDD
MUXOUT
DGND
Data Sheet
INPUT SHIFT REGISTER
The ADF4157 digital section includes a 5-bit RF R counter, a
12-bit RF N counter, and a 25-bit FRAC counter. Data is clocked
into the 32-bit input shift register on each rising edge of CLK.
The data is clocked in MSB first. Data is transferred from the
input shift register to one of five latches on the rising edge of
LE. The destination latch is determined by the state of the three
control bits (C3, C2, and C1) in the input shift register. These
are the three LSBs, DB2, DB1, and DB0, as shown in Figure 2.
The truth table for these bits is shown in Table 6. Figure 16
shows a summary of how the latches are programmed.
PROGRAM MODES
Table 6 and Figure 16 through Figure 21 show how to set up
the program modes in the ADF4157.
Several settings in the ADF4157 are double-buffered. These
include the LSB FRAC value, R counter value, reference doubler,
and current setting. This means that two events have to occur
before the part uses a new value of any of the double-buffered
settings. First, the new value is latched into the device by writing to
the appropriate register. Second, a new write must be performed
on Register 0, R0.
For example, updating the fractional value can involve a write
to the 13 LSB bits in R1 and the 12 MSB bits in R0. R1 should
be written to first, followed by the write to R0. The frequency
change begins after the write to R0. Double buffering ensures
that the bits written to in R1 do not take effect until after the
write to R0.
Table 6. C3, C2, and C1 Truth Table
Control Bits
C3 C2 C1 Register
0 0 0 Register 0 (R0)
0 0 1 Register 1 (R1)
0 1 0 Register 2 (R2)
0 1 1 Register 3 (R3)
1 0 0 Register 4 (R4)
Rev. D | Page 10 of 24
11 Page | ||
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