|
|
PDF ADF4151 Data sheet ( Hoja de datos )
| Número de pieza | ADF4151 | |
| Descripción | Fractional-N/Integer-N PLL Synthesizer | |
| Fabricantes | Analog Devices | |
| Logotipo |  |
|
Hay una vista previa y un enlace de descarga de ADF4151 (archivo pdf) en la parte inferior de esta página. Total 28 Páginas | ||
|
No Preview Available !
Data Sheet
Fractional-N/Integer-N PLL Synthesizer
ADF4151
FEATURES
GENERAL DESCRIPTION
Fractional-N synthesizer and integer-N synthesizer
RF bandwidth to 3.5 GHz
3.0 V to 3.6 V power supply
1.8 V logic compatibility
Separate charge pump supply (VP) allows extended tuning
voltage (up to 5.5 V) in 3 V systems
Programmable dual-modulus prescaler of 4/5 or 8/9
Programmable RF output phase
3-wire serial interface
Analog and digital lock detect
Switched bandwidth fast lock mode
Cycle slip reduction
APPLICATIONS
Wireless infrastructure (W-CDMA, TD-SCDMA, WiMax, GSM,
PCS, DCS, DECT)
Test equipment
Wireless LANs, CATV equipment
Clock generation
The ADF4151 allows implementation of fractional-N or
integer-N phase-locked loop (PLL) frequency synthesizers
if used with an external voltage controlled oscillator (VCO),
loop filter, and external reference frequency.
The ADF4151 is used with external VCO parts and is footprint
and software compatible with the ADF4350. The part consists
of a low noise digital phase frequency detector (PFD), a precision
charge pump, and a programmable reference divider. There is
a Σ-Δ based fractional interpolator to allow programmable
fractional-N division. The INT, FRAC, and MOD registers
define an overall N divider [N = (INT + (FRAC/MOD))]. The
RF output phase is programmable for applications that require
a particular phase relationship between the output and the
reference. The ADF4151 also features cycle slip reduction
circuitry, leading to faster lock times without the need for
modifications to the loop filter.
Control of all the on-chip registers is through a simple 3-wire
interface. The device operates with a power supply ranging
from 3.0 V to 3.6 V that can be powered down when not in use.
The ADF4151 is available in a 5 mm × 5 mm package.
FUNCTIONAL BLOCK DIAGRAM
SDVDD
AVDDx
DVDD
VP
RSET
REFIN
CLK
DATA
LE
×2
DOUBLER
10-BIT R
COUNTER
÷2
DIVIDER
DATA REGISTER
FUNCTION
LATCH
LOCK
DETECT
MULTIPLEXER
CHARGE
PUMP
PHASE
COMPARATOR
FLO SWITCH
MUXOUT
SW
LD
CPOUT
INTEGER FRACTION MODULUS
REG
REG
REG
THIRD-ORDER
FRACTIONAL
INTERPOLATOR
RFIN+
RFIN–
N COUNTER
ADF4151
CE AGND
Figure 1.
CPGND
SDGND
DGND
Rev. B
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibilityisassumedbyAnalogDevices for itsuse,nor foranyinfringementsofpatentsor other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarksandregisteredtrademarksarethepropertyoftheirrespectiveowners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
www.analog.com
Fax: 781.461.3113
©2011 Analog Devices, Inc. All rights reserved.
Free Datasheet http://www.datasheet4u.com/
1 page  
Data Sheet
ADF4151
TIMING CHARACTERISTICS
AVDD1, AVDD2 = DVDD = SDVDD = 3.3 V ± 10%; VP = AVDD to 5.5 V; AGND = DGND = 0 V; TA = TMIN to TMAX, unless otherwise noted.
Operating temperature range is −40°C to +85°C.
Table 2.
Parameter
t1
t2
t3
t4
t5
t6
t7
Limit (B Version)
20
10
10
25
25
10
20
Unit
ns min
ns min
ns min
ns min
ns min
ns min
ns min
Test Conditions/Comments
LE setup time
DATA to CLK setup time
DATA to CLK hold time
CLK high duration
CLK low duration
CLK to LE setup time
LE pulse width
CLK
t4 t5
DATA
DB31 (MSB)
t2 t3
DB30
DB2 (LSB)
(CONTROL BIT C3)
DB1 (LSB)
(CONTROL BIT C2)
LE
t1
LE
Figure 2. Timing Diagram
DB0 (LSB)
(CONTROL BIT C1)
t7
t6
Rev. B | Page 5 of 28
Free Datasheet http://www.datasheet4u.com/
5 Page 
Data Sheet
CIRCUIT DESCRIPTION
REFERENCE INPUT SECTION
The reference input stage is shown in Figure 14. SW1 and SW2
are normally closed switches. SW3 is normally open. When
power-down is initiated, SW3 is closed and SW1 and SW2 are
opened. This ensures that there is no loading of the REFIN pin
on power-down.
POWER-DOWN
CONTROL
NC 100kΩ
REFIN NC
SW2
SW1
NO
SW3
TO R COUNTER
BUFFER
Figure 14. Reference Input Stage
RF N DIVIDER
The RF N divider allows a division ratio in the PLL feedback
path. Division ratio is determined by the INT, FRAC, and MOD
values, which build up this divider.
INT, FRAC, MOD, AND R COUNTER RELATIONSHIP
The INT, FRAC, and MOD values, in conjunction with the R
counter, make it possible to generate output frequencies that
are spaced by fractions of the PFD frequency. See the RF
Synthesizer—A Worked Example section for more
information. The RF VCO frequency (RFOUT) equation is
RFOUT = fPFD × (INT + (FRAC/MOD))
(1)
where:
RFOUT is the output frequency of the external voltage controlled
oscillator (VCO).
INT is the preset divide ratio of the binary 16-bit counter
(23 to 32,767 for 4/5 prescaler, 75 to 65,535 for 8/9 prescaler).
FRAC is the numerator of the fractional division (0 to MOD − 1).
MOD is the preset fractional modulus (2 to 4095 for low noise
mode, 50 to 4095 for low spur mode).
fPFD = REFIN × [(1 + D)/(R × (1 + T))]
(2)
where:
REFIN is the reference input frequency.
D is the REFIN doubler bit.
R is the preset divide ratio of the binary 10–bit programmable
reference counter (1 to 1023).
T is the REFIN divide-by-2 bit (0 or 1).
ADF4151
FROM
VCO OUTPUT/
OUTPUT DIVIDERS
RF N DIVIDER
N COUNTER
INT
REG
N = INT + FRAC/MOD
TO PFD
THIRD-ORDER
FRACTIONAL
INTERPOLATOR
MOD
REG
FRAC
VALUE
Figure 15. RF INT Divider
INT N MODE
If the FRAC = 0 and DB8 in Register 2 (LDF) is set to 1, the
synthesizer operates in integer-N mode. The DB8 in Register 2
(LDF) should be set to 1 to get integer-N digital lock detect.
Additionally, lower phase noise is possible if the antibacklash
pulse width is reduced to 3 ns. This mode is not valid for
fractional-N applications.
R COUNTER
The 10-bit R counter allows the input reference frequency
(REFIN) to be divided down to produce the reference clock
to the PFD. Division ratios from 1 to 1023 are allowed.
PHASE FREQUENCY DETECTOR (PFD) AND
CHARGE PUMP
The phase frequency detector (PFD) takes inputs from the R
counter and N counter and produces an output proportional to
the phase and frequency difference between them. Figure 16 is
a simplified schematic of the phase frequency detector. The PFD
includes a programmable delay element that sets the width of
the antibacklash pulse, which can be either 6 ns (default, for
fractional-N applications) or 3 ns (for integer-N mode). This
pulse ensures that there is no dead zone in the PFD transfer
function and gives a consistent reference spur level.
HIGH
UP
D1 Q1
U1
+IN CLR1
DELAY
U3
CHARGE
PUMP
CP
HIGH
–IN
CLR2 DOWN
D2 Q2
U2
Figure 16. PFD Simplified Schematic
Rev. B | Page 11 of 28
Free Datasheet http://www.datasheet4u.com/
11 Page | ||
| Páginas | Total 28 Páginas | |
| PDF Descargar | [ Datasheet ADF4151.PDF ] | |
Hoja de datos destacado
| Número de pieza | Descripción | Fabricantes |
| ADF4150 | Fractional-N/Integer-N PLL Synthesizer | Analog Devices |
| ADF4150HV | Fractional-N/Integer-N PLL Synthesizer | Analog Devices |
| ADF4151 | Fractional-N/Integer-N PLL Synthesizer | Analog Devices |
| ADF4152HV | Fractional-N/ Integer N PLL Synthesizer | Analog Devices |
| Número de pieza | Descripción | Fabricantes |
| SLA6805M | High Voltage 3 phase Motor Driver IC. |
 Sanken |
| SDC1742 | 12- and 14-Bit Hybrid Synchro / Resolver-to-Digital Converters. |
Analog Devices |
|
DataSheet.es es una pagina web que funciona como un repositorio de manuales o hoja de datos de muchos de los productos más populares, |
| DataSheet.es | 2020 | Privacy Policy | Contacto | Buscar |