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PDF K4B2G0846B Data sheet ( Hoja de datos )
| Número de pieza | K4B2G0846B | |
| Descripción | 2Gb B-die DDR3 SDRAM | |
| Fabricantes | Samsung | |
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Rev. 1.41, Nov. 2010
K4B2G0446B
K4B2G0846B
K4B2G1646B
2Gb B-die DDR3 SDRAM
78 / 96 FBGA with Lead-Free & Halogen-Free
(RoHS compliant)
datasheet
SAMSUNG ELECTRONICS RESERVES THE RIGHT TO CHANGE PRODUCTS, INFORMATION AND
SPECIFICATIONS WITHOUT NOTICE.
Products and specifications discussed herein are for reference purposes only. All information discussed
herein is provided on an "AS IS" basis, without warranties of any kind.
This document and all information discussed herein remain the sole and exclusive property of Samsung
Electronics. No license of any patent, copyright, mask work, trademark or any other intellectual property
right is granted by one party to the other party under this document, by implication, estoppel or other-
wise.
Samsung products are not intended for use in life support, critical care, medical, safety equipment, or
similar applications where product failure could result in loss of life or personal or physical harm, or any
military or defense application, or any governmental procurement to which special terms or provisions
may apply.
For updates or additional information about Samsung products, contact your nearest Samsung office.
All brand names, trademarks and registered trademarks belong to their respective owners.
ⓒ 2010 Samsung Electronics Co., Ltd. All rights reserved.
-1-
Free Datasheet http://www.datasheet4u.com/
1 page  
K4B2G0446B
K4B2G0846B
K4B2G1646B
datasheet
1. Ordering Information
[ Table 1 ] Samsung 2Gb DDR3 B-die ordering information table
Organization
DDR3-800 (6-6-6)
DDR3-1066 (7-7-7)4
512Mx4
K4B2G0446B-HCF7
K4B2G0446B-HCF8
256Mx8
K4B2G0846B-HCF7
K4B2G0846B-HCF8
128Mx16
K4B2G1646B-HCF7
K4B2G1646B-HCF8
NOTE :
1. Speed bin is in order of CL-tRCD-tRP.
2. Backward Compatible to DDR3-1333(9-9-9), DDR3-1066(7-7-7), DDR3-800(6-6-6)
3. Backward Compatible to DDR3-1066(7-7-7), DDR3-800(6-6-6)
4. Backward Compatible to DDR3-800(6-6-6)
DDR3-1333 (9-9-9)3
K4B2G0446B-HCH9
K4B2G0846B-HCH9
K4B2G1646B-HCH9
Rev. 1.41
DDR3 SDRAM
DDR3-1600 (11-11-11)2
K4B2G0446B-HCK0
K4B2G0846B-HCK0
K4B2G1646B-HCK0
Package
78 FBGA
78 FBGA
96 FBGA
2. Key Features
[ Table 2 ] 2Gb DDR3 B-die Speed bins
Speed
DDR3-800
6-6-6
tCK(min)
2.5
CAS Latency
6
tRCD(min)
15
tRP(min)
15
tRAS(min)
37.5
tRC(min)
52.5
DDR3-1066
7-7-7
1.875
7
13.125
13.125
37.5
50.625
DDR3-1333
9-9-9
1.5
9
13.5
13.5
36
49.5
DDR3-1600
11-11-11
1.25
11
13.75
13.75
35
48.75
Unit
ns
nCK
ns
ns
ns
ns
• JEDEC standard 1.5V ± 0.075V Power Supply
• VDDQ = 1.5V ± 0.075V
• 400 MHz fCK for 800Mb/sec/pin, 533MHz fCK for 1066Mb/sec/pin,
667MHz fCK for 1333Mb/sec/pin, 800MHz fCK for 1600Mb/sec/pin
• 8 Banks
• Programmable CAS Latency(posted CAS): 5, 6, 7, 8, 9, 10, 11
• Programmable Additive Latency: 0, CL-2 or CL-1 clock
• Programmable CAS Write Latency (CWL) = 5 (DDR3-800), 6
(DDR3-1066), 7 (DDR3-1333) and 8 (DDR3-1600)
• 8-bit pre-fetch
• Burst Length: 8 (Interleave without any limit, sequential with starting
address “000” only), 4 with tCCD = 4 which does not allow seamless
read or write [either On the fly using A12 or MRS]
• Bi-directional Differential Data-Strobe
• Internal(self) calibration : Internal self calibration through ZQ pin
(RZQ : 240 ohm ± 1%)
• On Die Termination using ODT pin
• Average Refresh Period 7.8us at lower than TCASE 85°C, 3.9us at
85°C < TCASE < 95 °C
• Asynchronous Reset
• Package : 78 balls FBGA - x4/x8
96 balls FBGA - x16
• All of Lead-Free products are compliant for RoHS
• All of products are Halogen-free
The 2Gb DDR3 SDRAM B-die is organized as a 64Mbit x 4 I/Os x 8banks,
32Mbit x 8 I/Os x 8banks or 8Mbit x 16 I/Os x 8 banks device. This synchro-
nous device achieves high speed double-data-rate transfer rates of up to
1600Mb/sec/pin (DDR3-1600) for general applications.
The chip is designed to comply with the following key DDR3 SDRAM fea-
tures such as posted CAS, Programmable CWL, Internal (Self) Calibration,
On Die Termination using ODT pin and Asynchronous Reset .
All of the control and address inputs are synchronized with a pair of exter-
nally supplied differential clocks. Inputs are latched at the crosspoint of dif-
ferential clocks (CK rising and CK falling). All I/Os are synchronized with a
pair of bidirectional strobes (DQS and DQS) in a source synchronous fash-
ion. The address bus is used to convey row, column, and bank address
information in a RAS/CAS multiplexing style. The DDR3 device operates
with a single 1.5V ± 0.075V power supply and 1.5V ± 0.075V VDDQ.
The 2Gb DDR3 B-die device is available in 78ball FBGAs(x4/x8) and
96balls FBGA(x16).
NOTE : 1. This data sheet is an abstract of full DDR3 specification and does not cover the common features which are described in “DDR3 SDRAM Device Operation & Timing
Diagram”.
2. The functionality described and the timing specifications included in this data sheet are for the DLL Enabled mode of operation.
-5-
Free Datasheet http://www.datasheet4u.com/
5 Page 
K4B2G0446B
K4B2G0846B
K4B2G1646B
datasheet
Rev. 1.41
DDR3 SDRAM
4. Input/Output Functional Description
[ Table 3 ] Input/Output function description
Symbol
Type
Function
CK, CK
Input
Clock: CK and CK are differential clock inputs. All address and control input signals are sampled on the crossing of
the positive edge of CK and negative edge of CK. Output (read) data is referenced to the crossings of CK and CK
CKE
Input
Clock Enable: CKE HIGH activates, and CKE Low deactivates, internal clock signals and device input buffers and
output drivers. Taking CKE Low provides Precharge Power-Down and Self Refresh operation (all banks idle), or
Active Power-Down (Row Active in any bank). CKE is asynchronous for self refresh exit. After VREFCA has become
stable during the power on and initialization sequence, it must be maintained during all operations (including Self-
Refresh). CKE must be maintained high throughout read and write accesses. Input buffers, excluding CK, CK, ODT
and CKE are disabled during power-down. Input buffers, excluding CKE, are disabled during Self -Refresh.
CS
Input
Chip Select: All commands are masked when CS is registered HIGH. CS provides for external Rank selection on
systems with multiple Ranks. CS is considered part of the command code.
ODT
Input
On Die Termination: ODT (registered HIGH) enables termination resistance internal to the DDR3 SDRAM. When
enabled, ODT is only applied to each DQ, DQS, DQS and DM/TDQS, NU/TDQS (When TDQS is enabled via Mode
Register A11=1 in MR1) signal for x8 configurations. The ODT pin will be ignored if the Mode Register (MR1) is pro-
grammed to disable ODT.
RAS, CAS, WE
Input
Command Inputs: RAS, CAS and WE (along with CS) define the command being entered.
DM
(DMU), (DML)
Input
Input Data Mask: DM is an input mask signal for write data. Input data is masked when DM is sampled HIGH coinci-
dent with that input data during a Write access. DM is sampled on both edges of DQS. For x8 device, the function of
DM or TDQS/TDQS is enabled by Mode Register A11 setting in MR1.
BA0 - BA2
Input
Bank Address Inputs: BA0 - BA2 define to which bank an Active, Read, Write or Precharge command is being
applied. Bank address also determines if the mode register or extended mode register is to be accessed during a
MRS cycle.
A0 - A14
Input
Address Inputs: Provided the row address for Active commands and the column address for Read/Write commands
to select one location out of the memory array in the respective bank. (A10/AP and A12/BC have additional functions,
see below)
The address inputs also provide the op-code during Mode Register Set commands.
A10 / AP
Input
Autoprecharge: A10 is sampled during Read/Write commands to determine whether Autoprecharge should be per-
formed to the accessed bank after the Read/Write operation. (HIGH:Autoprecharge; LOW: No Autoprecharge)
A10 is sampled during a Precharge command to determine whether the Precharge applies to one bank (A10 LOW) or
all banks (A10 HIGH). if only one bank is to be precharged, the bank is selected by bank addresses.
A12 / BC
Input
Burst Chop:A12 is sampled during Read and Write commands to determine if burst chop(on-the-fly) will be per-
formed. (HIGH : no burst chop, LOW : burst chopped). See command truth table for details
RESET
DQ
Input
Input/Output
Active Low Asynchronous Reset: Reset is active when RESET is LOW, and inactive when RESET is HIGH.
RESET must be HIGH during normal operation. RESET is a CMOS rail to rail signal with DC high and low at 80% and
20% of VDD, i.e. 1.20V for DC high and 0.30V for DC low.
Data Input/ Output: Bi-directional data bus.
DQS, (DQS)
Input/Output
Data Strobe: Output with read data, input with write data. Edge-aligned with read data, centered in write data. For the
x16, DQSL: corresponds to the data on DQL0-DQL7; DQSU corresponds to the data on DQU0-DQU7. The data
strobe DQS, DQSL and DQSU are paired with differential signals DQS, DQSL and DQSU, respectively, to provide dif-
ferential pair signaling to the system during reads and writes. DDR3 SDRAM supports differential data strobe only and
does not support single-ended.
TDQS, (TDQS)
Output
Termination Data Strobe: TDQS/TDQS is applicable for X8 DRAMs only. When enabled via Mode Register A11=1 in
MR1, DRAM will enable the same termination resistance function on TDQS/TDQS that is applied to DQS/DQS. When
disabled via mode register A11=0 in MR1, DM/TDQS will provide the data mask function and TDQS is not used. x4/
x16 DRAMs must disable the TDQS function via mode register A11=0 in MR1.
NC No Connect: No internal electrical connection is present.
VDDQ
VSSQ
VDD
VSS
VREFDQ
VREFCA
ZQ
Supply
Supply
Supply
Supply
Supply
Supply
Supply
DQ Power Supply: 1.5V +/- 0.075V
DQ Ground
Power Supply: 1.5V +/- 0.075V
Ground
Reference voltage for DQ
Reference voltage for CA
Reference Pin for ZQ calibration
NOTE : Input only pins (BA0-BA2, A0-A14, RAS, CAS, WE, CS, CKE, ODT and RESET) do not supply termination.
- 11 -
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