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ADM1060 Schematic ( PDF Datasheet ) - Analog Devices

Teilenummer ADM1060
Beschreibung Communications System Supervisory/Sequencing Circuit
Hersteller Analog Devices
Logo Analog Devices Logo 




Gesamt 30 Seiten
ADM1060 Datasheet, Funktion
Communications System
Supervisory/Sequencing Circuit
ADM1060
FEATURES
Faults detected on 7 independent supplies
1 high voltage supply (2 V to 14.4 V)
4 positive voltage only supplies (2 V to 6 V)
2 positive/negative voltage supplies
(+2 V to +6 V and –2 V to –6 V)
Watchdog detector input—timeout delay programmable
from 200 ms to 12.8 sec
4 general-purpose logic inputs
Programmable logic block—combinatorial and sequencing
logic control of all inputs and outputs
9 programmable output drivers:
Open collector (external resistor required)
Open collector with internal pull-up to VDD
Fast internal pull-up to VDD
Open collector with internal pull-up to VPn
Fast internal pull-up to VPn
Internally charge-pumped high drive (for use with
external N-channel FETs—PDOs 1 to 4 only)
EEPROM—256 bytes of user EEPROM
Industry-standard 2-wire bus interface (SMBus)
Guaranteed PDO low with VPn, VH = 1 V
APPLICATIONS
Central office systems
Servers
Infrastructure network boards
High density, multivoltage system cards
GENERAL DESCRIPTION
The ADM1060 is a programmable supervisory/sequencing
device that offers a single chip solution for multiple power
supply fault detection and sequencing in communications
systems.
In central offices, servers, and other infrastructure systems, a
common backplane dc supply is reduced to multiple board sup-
plies using dc-to-dc converters. These multiple supplies are used
to power different sections of the board, such as 3.3 V logic
circuits, 5 V logic circuits, DSP core, and DSP I/O circuits. There
is usually a requirement that certain sections power up before
others; for example, a DSP core may need to power up before
the DSP I/O, or vice versa, to avoid damage, miscommunication,
or latch-up. The ADM1060 facilitates this, providing supply
fault detection and sequencing/combinatorial logic for up to
seven independent supplies. The seven supply fault detectors
consist of one high voltage detector (up to +14.4 V), two bipolar
voltage detectors (up to +6 V or down to −6 V), and four posi-
tive low voltage detectors (up to +6 V). All of the detectors can
be programmed to detect undervoltage, overvoltage, or out-of-
window (undervoltage or overvoltage) conditions. The inputs to
these supply fault detectors are via the VH (high voltage) pin,
VBn (positive or negative) pins, and VPn (positive only) pins.
Either the VH supply or one of the VPn supplies is used to
power the ADM1060 (whichever is highest). This ensures that
in the event of a supply failure, the ADM1060 is kept alive for as
long as possible, thus enabling a reliable fault flag to be asserted
and the system to be powered down in an ordered fashion.
Other inputs to the ADM1060 include a watchdog detector
(WDI) and four general-purpose inputs (GPIn). The watchdog
detector can be used to monitor a processor clock. If the clock
does not toggle (transition from low to high or from high to
low) within a programmable timeout period (up to 18 sec.), a
fail flag will assert. The four general-purpose inputs can be con-
figured as logic buffers or to detect positive/negative edges and
to generate a logic pulse or level from those edges. Thus, the
user can input control signals from other parts of the system
(e.g., RESET or POWER_GOOD) to gate the sequencing of the
supplies supervised by the ADM1060.
The ADM1060 features nine programmable driver outputs
(PDOs). All nine outputs can be configured to be logic outputs,
which can provide multiple functions for the end user such as
RESET generation, POWER_GOOD status, enabling of LDOs,
and watchdog timeout assertion. PDOs 1 to 4 have the added
feature of being able to provide an internally charge-pumped
high voltage for use as the gate drive of an external N-channel
FET that could be placed in the path of one of the supplies
being supervised.
(continued on Page 3)
.
Rev. B
Information furnished by Analog Devices is believed to be accurate and reliable.
However, no responsibility is assumed by Analog Devices for its use, nor for any
infringements of patents or other rights of third parties that may result from its use.
Specifications subject to change without notice. No license is granted by implication
or otherwise under any patent or patent rights of Analog Devices. Trademarks and
registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
www.analog.com
Fax: 781.326.8703 © 2003 Analog Devices, Inc. All rights reserved.






ADM1060 Datasheet, Funktion
ADM1060
SPECIFICATIONS
(VH = 4.75 V to 14.4 V, VPn = 3.0 V to 6.0 V,1 TA = −40°C to +85°C, unless otherwise noted.)
Table 1.
Parameter
POWER SUPPLY ARBITRATION
VDDCAP
POWER SUPPLY
Supply Current, IDD
Additional Current Available
from VDDCAP2
SUPPLY FAULT DETECTORS
Input Impedance
VH Input
VPn Inputs
VBn Inputs
Absolute Accuracy (VH, VPn, VBn Inputs)
Calibrated Absolute Accuracy3
VH, VPn Inputs
VBn Inputs
Glitch Filters (Digital)
PROGRAMMABLE DRIVER OUTPUTS
High Voltage (Charge Pump) Mode
(PDOs 1 to 4)
Output Impedance, ROUT
VOH
IOUTAVG
Standard (Digital Output) Mode
(PDOs 1 to 9)
VOH
VOL
ISINK2
RPULLUP- Weak Pull-Up
ISOURCE (VPn)2
Three-State Output Leakage Current
Min Typ Max Unit Test Conditions/Comments
2.7 V Any VPn ≥ 3.0 V
2.7 V VH ≥ 4.75 V
4.75 5.1 V Any VPn = 6.0 V
4.75 5.1 V VH = 14.4 V
3
5
1
mA VDDCAP = 4.75 V, no PDO FET drivers on, no
loaded PDO pull-ups to VDDCAP
mA VDDCAP = 4.75 V, all PDO FET drivers on (loaded
with 1 µA), no PDO pull-ups to VDDCAP
mA Max additional load that can be drawn from PDO
pull-ups to VDDCAP
52 kΩ From VH to GND
52 kΩ From VPn to GND
190 kΩ From VBn to 2.25 V (internal reference)
52 kΩ From VBn to GND (positive mode)
30 kΩ From VBn to GND (negative mode)
–2.5 +2.5 %
–1.0
+1.0 %
Factory preprogrammed to specific thresholds
–1.5
+1.5 %
Factory preprogrammed to specific thresholds
0 100 µs See Figure 19. Eight timeout options between 0 µs
and 100 µs
440 kΩ
11
12.5 14
V IOH = 0 µA
10.5 12
V IOH = 1 µA
20 µA 2 V < VOH < 7 V
2.4
VPU – 0.3
20
4.5
0.4
1.2
2.0
20
2
10
V VPU (pull-up to VDDCAP or VPn) > 2.7 V, IOH = 1 mA
V VPU to VPn = 6.0 V, IOH = 0 mA
V VPU ≤ 2.7 V, IOH = 1 mA
V IOL = 2 mA
V IOL = 10 mA
V IOL = 15 mA
mA Total sink current (PDO1–PDO9)
kΩ Internal pull-up
mA Current load on any VPn pull-up (i.e., total source
current available through any number of PDO
pull-up switches configured on to any one)
µA VPDO = 14.4 V
Rev. B | Page 5 of 52

6 Page









ADM1060 pdf, datenblatt
INPUTS
POWERING THE ADM1060
The ADM1060 is powered from the highest voltage input on
either the Positive Only supply inputs (VPn) or the High Volt-
age supply input (VH). The same pins are used for supply fault
detection (discussed below). A VDD arbitrator on the device
chooses which supply to use. The arbitrator can be considered
as diode OR’ing the positive supplies together (as shown in
Figure 17).The diodes are supplemented with switches in a syn-
chronous rectifier manner to minimize voltage loss. This loss
can be reduced to ~0.2 V, resulting in the ability to power the
ADM1060 from a supply as low as 3.0 V. Note that the supply on
the VBn pins cannot be used to power the device, even if the
input on these pins is positive. Also, the minimum supply of
3.0 V must appear on one of the VPn pins in order to correctly
power up the ADM1060. A supply of no less than 4.5 V can be
used on VH. This is because there is no synchronous rectifier
circuit on the VH pin, resulting in a voltage drop of ~1.5 V
across the diode of the VDD arbitrator.
An external capacitor to GND is required to decouple the
on-chip supply from noise. This capacitor should be connected
to the VDDCAP pin, as shown in Figure 17. The capacitor has
another use during “brown outs” (momentary loss of power).
Under these conditions, where the input supply, VPn, dips
transiently below VDD, the synchronous rectifier switch
immediately turns off so that it does not pull VDD down. The
VDD capacitor can then act as a reservoir to keep the chip active
until the next highest supply takes over the powering of the
device. A 1 µF capacitor is recommended for this function. A
minimum capacitor value of 0.1 µF is required.
Note that in the case where there are two or more supplies
within 100 mV of each other, the supply that takes control of
VDD first will keep control. For example, if VP1 is connected to a
3.3 V supply, VDD will power up to approximately 3.1 V through
VP1. If VP2 is then connected to another 3.3 V supply, VP1 will
still power the device, unless VP2 goes 100 mV higher than
VP1.
A second capacitor is required on the VCCP pin of the
ADM1060. This capacitor is the reservoir capacitor for the
central charge pump. Again, a 1 µF capacitor is recommended
for this function. A minimum capacitor value of 0.1 µF is
required.
ADM1060
VH
VDDCAP PIN
VP1
VP2
VP3
VP4
OFF-CHIP
DECOUPLING
CAPACITOR
ON-CHIP SUPPLY
Figure 17. VDD Arbitrator Operation
PROGRAMMABLE SUPPLY FAULT DETECTORS
(SFDs)
The ADM1060 has seven programmable supply fault detectors
(SFDs): one high voltage detector (+2 V to +14.4 V), two bipolar
detectors (+1 V to +6 V, −2 V to –6 V) and four positive only
voltage detectors (+0.6 V to +6 V). Inputs are applied to these
detectors via the VH (high voltage supply input), VBn (bipolar
supply input), and VPn (positive only input) pins, respectively.
The SFDs detect a fault condition on any of these input supplies.
A fault is defined as undervoltage (where the supply drops
below a preprogrammed level), overvoltage (where the supply
rises above a preprogrammed level), or out-of-window (where
the supply deviates outside either the programmed overvoltage
or undervoltage threshold). Only one fault type can be selected
at a time.
An undervoltage (UV) fault is detected by comparing the input
supply to a programmed reference (the undervoltage threshold).
If the input voltage drops below the undervoltage threshold, the
output of the comparator goes high, asserting a fault. The
undervoltage threshold is programmed using an 8-bit DAC. On
a given range, the UV threshold can be set with a resolution of
Step Size = Threshold Range/255
An overvoltage (OV) fault is detected in exactly the same way,
using a second comparator and DAC to program the reference.
All thresholds are programmed using 8-bit registers, one regis-
ter each for the seven UV thresholds and one each for the seven
OV thresholds. The UV or OV threshold programmed by the
user is given by
VT
= VR ×N
255
+VB
Rev. B | Page 11 of 52

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