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PDF LPC4370 Data sheet ( Hoja de datos )
| Número de pieza | LPC4370 | |
| Descripción | 32-bit ARM Cortex-M4 2 x M0 MCU 282 kB SRAM Ethernet | |
| Fabricantes | NXP Semiconductors | |
| Logotipo |  |
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LPC4370
32-bit ARM Cortex-M4 + 2 x M0 MCU; 282 kB SRAM; Ethernet;
two HS USBs; 80 Msps 12-bit ADC; configurable peripherals
Rev. 2 — 21 October 2013
Product data sheet
1. General description
The LPC4370 are ARM Cortex-M4 based microcontrollers for embedded applications
which include an ARM Cortex-M0 coprocessor and an ARM Cortex-M0 subsystem for
managing peripherals, 282 kB of SRAM, advanced configurable peripherals such as the
State Configurable Timer (SCT) and the Serial General Purpose I/O (SGPIO) interface,
two High-speed USB controllers, Ethernet, LCD, an external memory controller, and
multiple digital and analog peripherals including a high-speed 12-bit ADC. The LPC4370
operate at CPU frequencies of up to 204 MHz.
The ARM Cortex-M4 is a next generation 32-bit core that offers system enhancements
such as low power consumption, enhanced debug features, and a high level of support
block integration. The ARM Cortex-M4 CPU incorporates a 3-stage pipeline, uses a
Harvard architecture with separate local instruction and data buses as well as a third bus
for peripherals, and includes an internal prefetch unit that supports speculative branching.
The ARM Cortex-M4 supports single-cycle digital signal processing and SIMD
instructions. A hardware floating-point processor is integrated in the core.
The LPC4370 include an application ARM Cortex-M0 coprocessor and a second ARM
Cortex-M0 subsystem for managing the SGPIO and SPI peripherals. The ARM Cortex-M0
core is an energy-efficient and easy-to-use 32-bit core which is code- and tool-compatible
with the Cortex-M4 core. Both Cortex-M0 cores offer up to 204 MHz performance with a
simple instruction set and reduced code size.
2. Features and benefits
Main Cortex-M4 processor
ARM Cortex-M4 processor, running at frequencies of up to 204 MHz.
ARM Cortex-M4 built-in Memory Protection Unit (MPU) supporting eight regions.
ARM Cortex-M4 built-in Nested Vectored Interrupt Controller (NVIC).
Hardware floating-point unit.
Non-maskable Interrupt (NMI) input.
JTAG and Serial Wire Debug (SWD), serial trace, eight breakpoints, and four watch
points.
Enhanced Trace Module (ETM) and Enhanced Trace Buffer (ETB) support.
System tick timer.
Cortex-M0 coprocessor
ARM Cortex-M0 coprocessor capable of off-loading the main ARM Cortex-M4
processor.
Running at frequencies of up to 204 MHz.
Free Datasheet http://www.datasheet4u.com/
1 page  
NXP Semiconductors
LPC4370
32-bit ARM Cortex-M4/M0 microcontroller
4. Ordering information
Table 1. Ordering information
Type number
Package
Name
Description
Version
LPC4370FET256 LBGA256 Plastic low profile ball grid array package; 256 balls; body 17 17 1 mm SOT740-2
LPC4370FET100 TFBGA100 Plastic thin fine-pitch ball grid array package; 100 balls; body 9 9 0.7 mm SOT926-1
4.1 Ordering options
Table 2. Ordering options
Type number
LPC4370FET256 282 kB yes yes yes yes/yes 8/8 6
LPC4370FET100 282 kB no yes yes yes/no n/a 3
yes yes 164 LBGA256
no no 49 TFBGA100
LPC4370
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 2 — 21 October 2013
© NXP B.V. 2013. All rights reserved.
5 of 150
Free Datasheet http://www.datasheet4u.com/
5 Page 
NXP Semiconductors
LPC4370
32-bit ARM Cortex-M4/M0 microcontroller
Table 3. Pin description …continued
LCD, Ethernet, USB0, and USB1 functions are not available on all parts. See Table 2.
Symbol
Description
P1_10
P1_11
P1_12
P1_13
R8 H6
T9 J7
R9 K7
R10 H8
[3] I; PU I/O GPIO1[3] — General purpose digital input/output pin.
I U1_RI — Ring Indicator input for UART1.
O CTOUT_14 — SCT output 14. Match output 2 of timer 3.
I/O EMC_D3 — External memory data line 3.
- R — Function reserved.
- R — Function reserved.
- R — Function reserved.
I/O SD_DAT1 — SD/MMC data bus line 1.
[3] I; PU I/O GPIO1[4] — General purpose digital input/output pin.
I U1_CTS — Clear to Send input for UART1.
O CTOUT_15 — SCT output 15. Match output 3 of timer 3.
I/O EMC_D4 — External memory data line 4.
- R — Function reserved.
- R — Function reserved.
- R — Function reserved.
I/O SD_DAT2 — SD/MMC data bus line 2.
[3] I; PU I/O GPIO1[5] — General purpose digital input/output pin.
I U1_DCD — Data Carrier Detect input for UART1.
- R — Function reserved.
I/O EMC_D5 — External memory data line 5.
I T0_CAP1 — Capture input 1 of timer 0.
- R — Function reserved.
I/O SGPIO8 — General purpose digital input/output pin.
I/O SD_DAT3 — SD/MMC data bus line 3.
[3] I; PU I/O GPIO1[6] — General purpose digital input/output pin.
O U1_TXD — Transmitter output for UART1.
- R — Function reserved.
I/O EMC_D6 — External memory data line 6.
I T0_CAP0 — Capture input 0 of timer 0.
- R — Function reserved.
I/O SGPIO9 — General purpose digital input/output pin.
I SD_CD — SD/MMC card detect input.
LPC4370
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 2 — 21 October 2013
© NXP B.V. 2013. All rights reserved.
11 of 150
Free Datasheet http://www.datasheet4u.com/
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