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PDF NOIV1SN1300A Data sheet ( Hoja de datos )
| Número de pieza | NOIV1SN1300A | |
| Descripción | VITA 1300 1.3 Megapixel 150 FPS Global Shutter CMOS Image Sensor | |
| Fabricantes | ON Semiconductor | |
| Logotipo |  |
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NOIV1SN1300A,
NOIV2SN1300A
VITA 1300 1.3 Megapixel
150 FPS Global Shutter
CMOS Image Sensor
http://onsemi.com
Features
• SXGA: 1280 x 1024 Active Pixels
• 4.8 mm x 4.8 mm Pixel Size
• 1/2 inch Optical Format
• Monochrome (SN) or Color (SE)
• 150 Frames per Second (fps) at Full Resolution (LVDS)
• 37 Frames per Second (fps) at Full Resolution (CMOS)
• On-chip 10-bit Analog-to-Digital Converter (ADC)
• 8-bit or 10-bit Output Mode
• Four LVDS Serial Outputs or Parallel CMOS Output
• Random Programmable Region of Interest (ROI) Readout
• Pipelined and Triggered Global Shutter, Rolling Shutter
• On-chip Fixed Pattern Noise (FPN) Correction
• Serial Peripheral Interface (SPI)
• Automatic Exposure Control (AEC)
• Phase Locked Loop (PLL)
• High Dynamic Range (HDR)
• Dual Power Supply (3.3 V and 1.8 V)
• −40°C to +85°C Operational Temperature Range
• 48-pin LCC and Bare Die
• 475 mW Power Dissipation (LVDS)
• 290 mW Power Dissipation (CMOS)
• These Devices are Pb−Free and are RoHS Compliant
Figure 1. VITA 1300 Photograph
Applications
• Machine Vision
• Motion Monitoring
• Security
• Barcode Scanning (2D)
Description
The VITA 1300 is a 1/2 inch Super-eXtended Graphics Array (SXGA) CMOS image sensor with a pixel array of 1280 by 1024.
The high sensitivity 4.8 mm x 4.8 mm pixels support pipelined and triggered global shutter readout modes and can also be
operated in a low noise rolling shutter mode. In rolling shutter mode, the sensor supports correlated double sampling readout,
reducing noise and increasing the dynamic range.
The sensor has on-chip programmable gain amplifiers and 10-bit A/D converters. The integration time and gain parameters
can be reconfigured without any visible image artifact. Optionally the on-chip automatic exposure control loop (AEC) controls
these parameters dynamically. The image’s black level is either calibrated automatically or can be adjusted by adding a user
programmable offset.
A high level of programmability using a four wire serial peripheral interface enables the user to read out specific regions
of interest. Up to 8 regions can be programmed, achieving even higher frame rates.
The image data interface of the V1-SN/SE part consists of four LVDS lanes, facilitating frame rates up to 150 frames per
second. Each channel runs at 620 Mbps. A separate synchronization channel containing payload information is provided to
facilitate the image reconstruction at the receive end. The V2-SN/SE part provides a parallel CMOS output interface at reduced
frame rate.
The VITA 1300 is packaged in a 48-pin LCC package and is available in a monochrome and color version.
Contact your local ON Semiconductor office for more information.
© Semiconductor Components Industries, LLC, 2013
June, 2013 − Rev. 9
1
Publication Order Number:
NOIV1SN1300A/D
Free Datasheet http://www.datasheet4u.com/
1 page  
NOIV1SN1300A, NOIV2SN1300A
Table 5. ELECTRICAL SPECIFICATIONS
Boldface limits apply for TJ = TMIN to TMAX, all other limits TJ = +30°C. (Notes 5, 6 and 7)
Parameter
Description
Min Typ Max
Power Supply Parameters - V1-SN/SE LVDS
vdd_33
Supply voltage, 3.3 V
3.0 3.3 3.6
Idd_33
Current consumption 3.3 V supply
90 110 130
vdd_18
Supply voltage, 1.8 V
1.6 1.8 2.0
Idd_18
Current consumption 1.8 V supply
45 60 75
vdd_pix
Supply voltage, pixel
3.0 3.3 3.6
Idd_pix
Current consumption pixel supply
0.8 1.8 2.5
Ptot Total power consumption at vdd_33 = 3.3 V, vdd_18 = 1.8 V
375 475 575
Pstby_lp
Power consumption in low power standby mode. See Silicon Errata
on page 66
50
Popt
Power consumption at lower pixel rates
Configurable
Power Supply Parameters - V2-SN/SE CMOS
vdd_33
Supply voltage, 3.3 V
3.0 3.3 3.6
Idd_33
Current consumption 3.3 V supply
70 90 110
vdd_18
Supply voltage, 1.8 V
1.6 1.8 2.0
Idd_18
Current consumption 1.8 V supply
4 7 10
vdd_pix
Supply voltage, pixel
3.0 3.3 3.6
Idd_pix
Current consumption pixel supply
0.5 1
Ptot Total power consumption
220 290 360
Pstby_lp
Power consumption in low power standby mode. See Silicon Errata
on page 66
50
Popt
Power consumption at lower pixel rates
Configurable
I/O - V2-SN/SE CMOS (JEDEC- JESD8C-01): Conforming to standard/additional specifications and deviations listed
fpardata
Data rate on parallel channels (10-bit)
62
Cout
Output load (only capacitive load)
10
tr Rise time (10% to 90% of input signal)
2.5 4.5 6.5
tf Fall time (10% to 90% of input signal)
2 3.5 5
I/O - V1-SN/SE LVDS (EIA/TIA-644): Conforming to standard/additional specifications and deviations listed
fserdata
Data rate on data channels
DDR signaling - 4 data channels, 1 synchronization channel;
620
fserclock
Clock rate of output clock
Clock output for mesochronous signaling
310
Vicm
LVDS input common mode level
0.3 1.25 2.2
Tccsk
Channel to channel skew (Training pattern allows per channel skew
correction)
50
V1-SN/SE LVDS Electrical/Interface
fin Input clock rate when PLL used
62
fin Input clock when LVDS input used
310
tidc Input clock duty cycle when PLL used
40 50 60
tj Input clock jitter
20
fspi SPI clock rate when PLL used at fin = 62 MHz
10
V2-SN/SE CMOS Electrical/Interface
fin Input clock rate
62
Units
V
mA
V
mA
V
mA
mW
mW
V
mA
V
mA
V
mA
mW
mW
Mbps
pF
ns
ns
Mbps
MHz
V
ps
MHz
MHz
%
ps
MHz
MHz
http://onsemi.com
5
Free Datasheet http://www.datasheet4u.com/
5 Page 
NOIV1SN1300A, NOIV2SN1300A
Column Multiplexer
All pixels of one image row are stored in the column
sample-and-hold (S/H) stages. These stages store both the
reset and integrated signal levels.
The data stored in the column S/H stages is read out
through 8 parallel differential outputs operating at a
frequency of 31 MHz.
At this stage, the reset signal and integrated signal values
are transferred into an FPN-corrected differential signal.
The column multiplexer also supports read-1-skip-1 and
read-2-skip-2 mode. Enabling this mode can speed up the
frame rate, with a decrease in resolution.
Bias Generator
The bias generator generates all required reference
voltages and bias currents that the on-chip blocks use. An
external resistor of 47 kW, connected between pin
IBIAS_MASTER and gnd_33, is required for the bias
generator to operate properly.
Analog Front End
The AFE contains 8 channels, each containing a PGA and
a 10-bit ADC.
For each of the 8 channels, a pipelined 10-bit ADC is used
to convert the analog image data into a digital signal, which
is delivered to the data formatting block. A black calibration
loop is implemented to ensure that the black level is mapped
to match the correct ADC input level.
Data Formatting
The data block receives data from two ADCs and
multiplexes this data to one data stream. A cyclic
redundancy check (CRC) code is calculated on the passing
data.
A frame synchronization data block is foreseen to transmit
synchronization codes such as frame start, line start, frame
end, and line end indications.
The data block calculates a CRC once per line for every
channel. This CRC code can be used for error detection at the
receiving end.
Serializer and LVDS Interface (V1−SN/SE only)
The serializer and LVDS interface block receives the
formatted (10-bit or 8-bit) data from the data formatting
block. This data is serialized and transmitted by the LVDS
output driver.
In 10-bit mode, the maximum output data rate is 620 Mbps
per channel. In 8-bit mode, the maximum output data rate is
496 Mbps per channel.
In addition to the LVDS data outputs, two extra LVDS
outputs are available. One of these outputs carries the output
clock, which is skew aligned to the output data channels. The
second LVDS output contains frame format synchronization
codes to serve system-level image reconstruction.
Output MUX (V2−SN/SE only)
The output MUX multiplexes the four data channels to
one channel and transmits the data words using a 10-bit
parallel CMOS interface.
Frame synchronization information is communicated by
means of frame and line valid strobes.
Sequencer
The sequencer:
• Controls the image core. Starts and stops integration in
rolling and global shutter modes and control pixel
readout.
• Operates the sensor in master or slave mode.
• Applies the window settings. Organizes readouts so that
only the configured windows are read.
• Controls the column multiplexer and analog core.
Applies gain settings and subsampling modes at the
correct time, without corrupting image data.
• Starts up the sensor correctly when leaving standby
mode.
Automatic Exposure Control
The AEC block implements a control system to modulate
the exposure of an image. Both integration time and gains
are controlled by this block to target a predefined
illumination level.
http://onsemi.com
11
Free Datasheet http://www.datasheet4u.com/
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