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PDF RTL8671B Data sheet ( Hoja de datos )
| Número de pieza | RTL8671B | |
| Descripción | Integrated ADSL2+ Router Controller | |
| Fabricantes | Realtek | |
| Logotipo |  |
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RTL8671B/ RTL8671BH
Integrated ADSL2+ Router Controller
Datasheet
Rev. 0.4
6 May, 2008
Track ID: xxxx-nnnn-nn
Integrated ADSL2+ Router Controller
i
Track ID: xxxx-nnnn-nn Rev. 0.4
Free Datasheet http://www.datasheet4u.com/
1 page  
RTL8671B/ RTL8671BH
Datasheet
1. General Description
The Realtek RTL8671B/ RTL8671BH are integrated SoC featuring a RISC, an ADSL2+ Discrete
Multi-tone (DMT) data-pump, a hardware-based ATM Segmentation and Reassembly (SAR),
two 10/100Mbps IEEE 802.3 compliant MACs with an embedded Ethernet transceiver, and a
USB PHY port. Mated with the Realtek RTL8271B (ADSL2+ Analog Front End), RTL8671B/
RTL8671BH provide a low cost integrated solution for ADSL2+ CPE modems, routers, or
gateways.
RTL8671B/ RTL8671BH encompass high-performance DSP technologies, optimized mix-signal
designs, and an efficient architecture to provide a seamless WAN to LAN router controller. The
embedded RISC network processor supports the MIPS I instruction set along with DSP
extensions and achieves a 340MHz clock rate in a six-stage pipeline to support layer 2, 3, and
other upper layer applications.
The DMT engine supports the upstream data rate from 32kbp to above 3Mbps and the
downstream data rate from 32kbps to above 24Mbps throughput, and complies with:
n ANSI T1.413 Issue 2
n ITU-T G.992.1 (G..dmt) Annexes A and B
n G.992.2 (G..lite) Annexes A and B
n G.992.3 ADSL2 (G.dmt.bis) Annexes A, B, I, J, L, and M
n G.992.4 ADSL2 (G.lite.bis)
n G.992.5 ADSL2+
The Ethernet interface offers high-speed transmission over CAT-5 UTP cable or CAT-3 UTP
(10Mbps only) cable. Ethernet functions such as Crossover Detection & Auto-Correction and
polarity correction are implemented to provide robust transmission and reception capability at
high speeds.
Integrated ADSL2+ Router Controller
1
Track ID: xxxx-nnnn-nn Rev. 0.4
Free Datasheet http://www.datasheet4u.com/
5 Page 
U1DP, U1DM
20, 19
I/O
U1ID (NC)
U1VBUS
USBLED1
ENUSBOTG
AFPWDN
AFRXD[3:0]
AFTXD[3:0]
21 I
22 I
54 O
114 O
AFE Interface
40 O
34, 33, 32, 31
I
30, 29, 28, 27
O
AFCLWD
CKIN
AFCTRL
VREF
MD[15:0]
MA[22:0]
35 I
11 I
37 O
128 I
Memory Bus
95, 96, 97, 98, 100, 101, 103, 104,
I/O
105, 106, 108, 110, 112, 115, 116, 117
59, 61, 62, 64, 65, 66, 67, 68, 69, 70,
O
72, 73, 74, 75, 76, 78, 79, 80, 81, 83,
84, 85, 86
Integrated ADSL2+ Router Controller
6
RTL8671B/ RTL8671BH
Datasheet
Differential data I/O of USB PHY 1
To RTL8671BH: either host/device
mode supported; configured by
U1ID
To RTL8671B: device mode
supported only
To RTL8671BH: Pull-low/high to
select PHY 1 as host/device
To RTL8671B: NC
USB VBUS detect pin; used for
PHY 1 configured in device mode
USB LED driver output
Enable USB OTG block
Power down control to AFE
Data input from AFE
Data output to AFE
Pins AFTXD[3:2] strap into register
values as OCCLK_SEL[1:0], which
defines the CPU speed. For
RTL8671B/ RTL8671BH, the
AFTXD[3:2] should be strictly
pulled as ‘10’.[1]
Word clock input from AFE
Master clock from AFE
Control data output to AFE
Dying Gasp voltage detect input
Data for SDRAM, parallel Flash,
and ROM
Address for SDRAM and Flash.
Pins MA[10:8] strap into register
values as OCCLK_SEL[4:2], which
defines the CPU speed. For
RTL8671B/ RTL8671BH, the
MA[10:8] should be strictly pulled
as ‘001’.[1]
Track ID: xxxx-nnnn-nn Rev. 0.4
Free Datasheet http://www.datasheet4u.com/
11 Page | ||
| Páginas | Total 27 Páginas | |
| PDF Descargar | [ Datasheet RTL8671B.PDF ] | |
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