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PDF ANX7150 Data sheet ( Hoja de datos )
| Número de pieza | ANX7150 | |
| Descripción | Zero Power HDMI 1.3 Transmitter | |
| Fabricantes | Analogix | |
| Logotipo |  |
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Hay una vista previa y un enlace de descarga de ANX7150 (archivo pdf) en la parte inferior de esta página. Total 33 Páginas | ||
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Preliminary
ANX7150
Zero Power HDMI® 1.3 Transmitter
HDMI 1.3 compatible transmitter with patented
Zero power HDMI transmitter technology
Optional HDCP function with internal keys
Supports link date rates up to 165Mpixel/sec
Flexible video pixel input interface, supports
DVD and HD MPEG decoders
- 24-bit RGB/YCbCr 4:4:4
- 16/20/24-bit YCbCr 4:2:2
- 8/10/12-bit YC Mux(ITU 601 and 656)
A CoolHD™ family product
Backward compatible with DVI1.1
Programmable output swing
6KV ESD performance
RoHS compliant and Halogen free package
Package offered
- 48-pin QFN
- 80-pin LQFP
- 81-pin VFBGA
- 81-pin TFBGA
- YCbCr-to-RGB colour space conversion
- YCbCr 4:2:2 to 4:4:4 up-sample
- 12-bit, dual-edge clocking input mode
- 8-bit DDR YCMux (ITU 601 and 656)
Advanced digital audio interface
- 8-channel I2S support Dolby Digital and
DVD-Audio
- Up to 6 channels 1-bit super audio support
- S/PDIF supports PCM, Dolby Digital and DTS
digital audio transmission
- IEC 60958 or 61937 compatible
- 2:1 and 4:1 down-sample to handle 96 KHz and
192 KHz audio stream
ANX7150, a CoolHD™ family product, it is a
revolutionary breakthrough technology that makes a
zero power HDMI transmitter a reality. CoolHD™
technology solves the problem by recovering power
from the HDMI link that is normally wasted as heat
and using it to power the HDMI transmitter. This
technology is transforming the mobile and handheld
markets.
ANX7150 can be ordered with an optional HDCP 1.2
function (including internal keys) to support content
protection.
Built-in video pattern generator and audio tone
generator are included for system self-test.
Power requirement is 1.8V and 3.3V.
Software-controlled power management
For package and HDCP options, refer to the parts
ordering information.
DATA_CLK
D
VSYNC
HSYNC
DE
SCK/SAUD_CLK
SDO/SAUD0
SD1/SAUD1
SD2/SAUD2
SD3/SAUD3
WS/SAUD4
MCLK
SPDIF/SAUD5
CSDA
CSCL
INTP
PLL
Video Data Capture
DE Gen BIST
4:2:2 to 4:4:4
YCbCr to RGB
Audio Data Capture
BIST
I2C
Slave
Auxiliary
Packet Gen
HDCP Key
ROM
HDCP
Authorization
& Encryption
Configuration
Registers
DDC Bridge
Optional HDCP
Function
TMDS
Tx
DDC
Master
TX0_P/N
TX1_P/N
TX2_P/N
TXC_P/N
R_BIAS
HPD
DSCL
DSDA
ANX7150 Block Diagram
Free Datasheet http://www.datasheet4u.com/
1 page  
Preliminary
ANX7150
1
A
VOREG
2
2
TX1P
B TX2N AVSSP
C TX2P SSCL
3
TX1N
AVSS
REXT
4
VOREG
1
5
TX0P
6
TX0N
7
AVSS
VOREG
0
GPIO
TEST_E
N
AVSS
NC
SPDIF/
SAUD5
HPD
DVSS
89
TXCP TXCN A
INTP/
ADDR_
SEL
VOREG
C
B
DSDA DSCL C
D VCOP
SSDA
RESET_
N
DVSS
DVDD18 DVDD18
DVSS
MCLK
WS/SAU
D4
D
E
VCON
DATA_C
LK
DVDD18
DVSS
DVSS
F D0
D1 DVDD33 DVDD33 DVSS
DVSS
DVDD33
SD2/SAI
D2
SD3/SA
UD3
E
DVSS
SCK/
SAUD_
CLK
SD0/SAI
D0
SD1/SA
UD1
F
G D2 D3 D4 DVDD18 D12 DVDD18 D23 D22 D21 G
H D5
D6 HSYNC D9
D11 D14 D16 D18 D20 H
J D7 VSYNC DE
123
D8 D10 D13 D15
4567
Figure 2-3 ANX7150 81-pin VFBGA
D17
8
D19
9
J
Page 5 of 33
Analogix Confidential
Rev 1.3
Free Datasheet http://www.datasheet4u.com/
5 Page 
Preliminary
ANX7150
Table 3-6 Slave I2C DC Specifications
Symbol
Parameter
VIN Input voltage range
VIL Low level input voltage
VIH High level input voltage
VOL Low level output voltage
IIL Input leakage current (Hi-Z)
ZOUT Output impedance
CIN Input capacitance
CL I2C signal load capacitance
Min
-0.25
--
0.8
--
--
--
--
--
Typ Max Units
-- 3.6 V
-- 0.3 V
-- -- V
-- 0.2 V
-- 50 uA
-- 50 ohms
-- 3.0 pF
-- 20 pF
3.4 AC Specifications
3.4.1 HDMI Output Timing
These specifications apply under normal operating conditions with output pin load CL = 10 pF unless otherwise
stated.
Table 3-7 HDMI Output Timings
Symbol
Parameter
Min Typ
Max Units
SLH
TMDS differential output rise time (20%-80%) 1
100
ps
0.25
TBIT 2
SHL
TMDS differential output fall time (80%-20%)
80
ps
0.2 TBIT
TSDF Delay from DE falling edge to VSYNC or HSYNC rising edge 1
TCP
TSDR Delay from VSYNC or HSYNC falling edge to DE rising edge 1
TCP
1. Limits are defined by the HDMI Specification.
2. TBIT is the time required to carry a single bit across an HDMI channel, and is governed by the active input clock. (10 x TBIT) =
TCP
3.4.2 Digital Video Data Input Timing
These specifications apply under normal operating conditions with output pin load CL = 10 pF unless otherwise
stated.
Table 3-8 Digital Video Input Timing
Symbol
Parameter
Min Typ
Max Units
TCDC DATA_CLK input duty cycle 15 85 %
TCJ DATA_CLK input peak-to-peak jitter tolerance 1
2 ns
Single-edge clock mode (one pixel per clock)
TCP
Clock period of DATA_CLK
5.56 40 ns
fCP
Clock frequency of DATA_CLK
25 180 MHz
TDSF
Data set-up time to DATA_CLK falling edge
0.6
ns
TDHF Data hold time from DATA_CLK falling edge 1
ns
TDSR
Data set-up time to DATA_CLK rising edge
0.6
TDHR Data hold time from DATA_CLK rising edge 1
ns
ns
Dual-edge clock mode (DDR Mode)
TCPD
Clock period of DATA_CLK, DDR input mode
11.12
fCPD
Clock frequency of DATA_CLK, DDR input mode
12.5
80 ns
90 MHz
Page 11 of 33
Analogix Confidential
Rev 1.3
Free Datasheet http://www.datasheet4u.com/
11 Page | ||
| Páginas | Total 33 Páginas | |
| PDF Descargar | [ Datasheet ANX7150.PDF ] | |
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