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8S003F3 Schematic ( PDF Datasheet ) - STMicroelectronics

Teilenummer 8S003F3
Beschreibung STM8S003F3
Hersteller STMicroelectronics
Logo STMicroelectronics Logo 




Gesamt 30 Seiten
8S003F3 Datasheet, Funktion
STM8S003F3 STM8S003K3
Value line, 16 MHz STM8S 8-bit MCU, 8 Kbyte Flash, 128 byte data
EEPROM, 10-bit ADC, 3 timers, UART, SPI, I²C
Datasheet - production data
Features
Core
16 MHz advanced STM8 core with Harvard
architecture and 3-stage pipeline
Extended instruction set
Memories
Program memory: 8 Kbyte Flash memory; data
retention 20 years at 55 °C after 100 cycles
RAM: 1 Kbyte
Data memory: 128 bytes true data EEPROM;
endurance up to 100 k write/erase cycles
Clock, reset and supply management
2.95 V to 5.5 V operating voltage
Flexible clock control, 4 master clock sources
– Low-power crystal resonator oscillator
– External clock input
– Internal, user-trimmable 16 MHz RC
– Internal low-power 128 kHz RC
Clock security system with clock monitor
Power management
– Low-power modes (wait, active-halt, halt)
– Switch-off peripheral clocks individually
– Permanently active, low-consumption
power-on and power-down reset
Interrupt management
Nested interrupt controller with 32 interrupts
Up to 27 external interrupts on 6 vectors
LQFP32
7x7 mm
TSSOP20
6.5x6.4 mm
UFQFPN20
3x3 mm
Timers
Advanced control timer: 16-bit, 4 CAPCOM
channels, 3 complementary outputs, dead-time
insertion and flexible synchronization
16-bit general purpose timers, with 3 CAPCOM
channels (IC, OC or PWM)
8-bit basic timer with 8-bit prescaler
Auto wakeup timer
Window and independent watchdog timers
Communications interfaces
UART with clock output for synchronous
operation, SmartCard, IrDA, LIN master mode
SPI interface up to 8 Mbit/s
I2C interface up to 400 Kbit/s
Analog to digital converter (ADC)
10-bit ADC, ± 1 LSB ADC with up to 5
multiplexed channels, scan mode and analog
watchdog
I/Os
Up to 28 I/Os on a 32-pin package including 21
high-sink outputs
Highly robust I/O design, immune against
current injection
Development support
Embedded single-wire interface module
(SWIM) for fast on-chip programming and non-
intrusive debugging
April 2016
This is information on a product in full production.
DocID018576 Rev 8
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8S003F3 Datasheet, Funktion
List of tables
STM8S003F3 STM8S003K3
Table 49.
Table 50.
Table 51.
Table 52.
Table 53.
Table 54.
Table 55.
Table 56.
EMI data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86
ESD absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86
Electrical sensitivities . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87
LQFP32 - 32-pin, 7 x 7 mm low-profile quad flat package mechanical data. . . . . . . . . . . . 89
TSSOP20 – 20-lead thin shrink small outline, 6.5 x 4.4 mm, 0.65 mm pitch,
package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91
UFQFPN20 - 20-lead, 3 x3 mm, 0.5 mm pitch, ultra thin fine pitch quad flat
package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95
Thermal characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97
Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102
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DocID018576 Rev 8

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8S003F3 pdf, datenblatt
Product overview
4 Product overview
STM8S003F3 STM8S003K3
The following section intends to give an overview of the basic features of the
STM8S003F3/K3 value line functional modules and peripherals.
For more detailed information please refer to the corresponding family reference manual
(RM0016).
4.1 Central processing unit STM8
The 8-bit STM8 core is designed for code efficiency and performance.
It contains six internal registers which are directly addressable in each execution context, 20
addressing modes including indexed indirect and relative addressing and 80 instructions.
Architecture and registers
Harvard architecture
3-stage pipeline
32-bit wide program memory bus - single cycle fetching for most instructions
X and Y 16-bit index registers - enabling indexed addressing modes with or without
offset and read-modify-write type data manipulations
8-bit accumulator
24-bit program counter - 16-Mbyte linear memory space
16-bit stack pointer - access to a 64 K-level stack
8-bit condition code register - 7 condition flags for the result of the last instruction
Addressing
20 addressing modes
Indexed indirect addressing mode for look-up tables located anywhere in the address
space
Stack pointer relative addressing mode for local variables and parameter passing
Instruction set
80 instructions with 2-byte average instruction size
Standard data movement and logic/arithmetic functions
8-bit by 8-bit multiplication
16-bit by 8-bit and 16-bit by 16-bit division
Bit manipulation
Data transfer between stack and accumulator (push/pop) with direct stack access
Data transfer using the X and Y registers or direct memory-to-memory transfers
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