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IR1155S Schematic ( PDF Datasheet ) - International Rectifier

Teilenummer IR1155S
Beschreibung uPFC ONE CYCLE CONTROL PFC IC
Hersteller International Rectifier
Logo International Rectifier Logo 




Gesamt 21 Seiten
IR1155S Datasheet, Funktion
Feb 28, 2011
IR1155S
PROGRAMMABLE FREQUENCY, ONE CYCLE CONTROL PFC IC
Features
• PFC IC with IR proprietary “One Cycle Control”
• Continuous conduction mode boost type PFC
• Programmable switching frequency (48k-200kHz)
• Average current mode control
• Output overvoltage protection
• Open loop protection
• Cycle by cycle peak current limit
• VCC under voltage lockout
• Programmable soft start
• Micropower startup
• User initiated micropower “Sleep Mode”
• OVP/EN pin internal filtering for higher noise immunity
• 1.5A peak gate drive
• Latch immunity and ESD protection
Description
The μPFC IR1155 power factor correction IC, based on IR proprietary "One
Cycle Control" (OCC) technique, provides for high PF, low THD and
excellent DC Bus regulation while enabling drastic reduction in component
count, PCB area and design time as compared to traditional solutions. The
IC is designed to operate in continuous conduction mode Boost PFC
converters with average current mode control over 85-264VAC input line
voltage range. Switching frequency can be programmed to anywhere
between 48kHz to 200kHz based on the specific application requirement.
In addition, IR1155 offers several advanced system-enabling and protective
features such as dedicated pin for over voltage protection, cycle by cycle
peak current limitation, open loop protection, VCC UVLO, soft-start and
micropower startup/sleep-mode with IC current consumption less than
200µA. The sleep mode, invoked by pulling the OVP/EN pinhttp://www.DataSheet4U.com/ low, enables
compliance with standby power requirements mandated by regulations
such as Energy Star, Green Power, Blue Angel etc.
Package
IR1155 Application Diagram
AC LINE
-
+
AC NEUTRAL
VOUT
1 COM GATE 8
2 FREQ VCC 7
3 ISNS VFB 6
4 OVP COMP 5
IR1155S
VCC
RTN
www.irf.com
© 2011 International Rectifier






IR1155S Datasheet, Funktion
IR1155S
Current Amplifier Section
Parameter
Symbol
DC Gain
Corner Frequency
Input Offset Voltage
ISNS Bias Current
Blanking Time
gDC
fC
VIO
IISNS(Bias)
TBLANK
Min.
-57
220
Typ.
3.1
5
4
370
Max.
16
-13
520
Units
V/V
kHz
mV
µA
ns
Remarks
- Average current mode, Note 1
Note 1
Gate Driver Section
Parameter
Gate Low Voltage
Symbol
VGLO
Gate High Voltage
VGTH
Rise Time
Fall Time
Output Peak Current
Gate Voltage @ Fault
tr
tf
IOPK
VG fault
Min.
12
10
1.5
Typ.
13
20
20
Max.
0.8
14
0.08
http://www.DataSheet4U.com/
Note 1 – Guaranteed by design, but Not tested in production
Units
V
V
V
ns
ns
A
V
Remarks
IGATE=200mA
Internal Gate clamp
VCC = 11.5V
CLOAD = 1nF
CLOAD = 1nF
CLOAD = 10nF, Note 1
IGATE = 20mA
www.irf.com
6 © 2011 International Rectifier

6 Page









IR1155S pdf, datenblatt
IR1155S
IR1155 General Description
Programmable Soft Start
The soft start process controls the rate of rise of
the voltage feedback loop error signal thus
providing a linear control on RMS input current
that the PFC converter will admit. The soft start
time is essentially controlled by voltage error
amplifier compensation components selected and
is therefore user programmable to some degree
based on desired loop crossover frequency.
Gate Drive Capability
The gate drive output stage of the IC is a totem
pole driver with 1.5A peak current drive
capability. The gate drive is internally clamped at
13V (Typ). Gate drive buffer circuits can be easily
driven with the GATE pin of the IC to suit any
system power level.
System Protection Features
IR1155 protection features include DC bus
Overvoltage protection (OVP) via a dedicated pin,
Open-loop protection (OLP), Cycle-by-cycle peak
current limit (IPK LIMIT), Soft-current limit and
VCC under voltage lock-out (UVLO).
- Overvoltage voltage protection (OVP) feature in
IR1155 is achieved using a dedicated pin called
the OVP/EN pin. The input of OVP comparator is
connected the OVP pin. When the OVP pin
voltage exceeds VOVP, an overvoltage situation is
detected and the gate drive is immediately
terminated. The gate drive is re-enabled only
after OVP pin voltage drops below VOVP(RST). The
use of a dedicated OVP/EN pin ensures that the
system is protected from catastrophic
overvoltages, even if the feed-back loop
(connected to the VFB pin) encounters any
failure. This ensures the best possible system
overvoltage protection against extremes of
situations.
- Open Loop Protection (OLP) is activated
whenever the VFB pin voltage falls below VOLP
threshold. The gate drive is then immediately
disabled, VCOMP is actively discharged and the
IC is pushed into Stand-by mode. The IC will re-
start (with soft-start) once the VFB pin voltage
exceeds VOLP again. There is no voltage
hysteresis associated with this feature. During
start-up the IC is held in Stand-by until this pin
exceeds VOLP.
- Soft-current limit is an output voltage fold-back type
protection feature that is encountered when the RMS
current in the PFC converter exceeds a certain
magnitude that causes the internal error signal of the
voltage feedback, Vm to saturate at its highest value.
Amplitude of Vm signal is directly proportional to the
RMS input current admitted into the PFC converter.
In effect, once Vm saturates, the maximum RMS
current admissible into the PFC converter has been
encountered. Any attempt to increase the RMS
current beyond this limit causes the IC to limit the
duty cycle delivered to the PFC converter, which then
has the effect of causing the DC bus voltage to droop
i.e. output voltage folds-back. The current level at
which Vm saturates is closely related to the value of
the current sense resistor selected for the PFC
converter. In one way, this feature can be perceived
to offer an overpower limitation of sorts at the
conditions at which current sense design is
performed (minimum VAC & maximum output
power). For details, please refer to IR1155
Application Note.
- Cycle-by-cycle peak current limit protection
instantaneously turns-off the gate output whenever
the ISNS pin voltage exceeds VISNS(PK) threshold in
magnitude. The gate drive output is re-enabled onlyhttp://www.DataSheet4U.com/
after the magnitude of the ISNS pin voltage drops
below the VISNS(PK) threshold. It is clarified that even
though the IC operates based on average current
mode control, since the averaging circuit is
decoupled from the peak current limit comparator
input, the IC is still able to provide instantaneous
response to a system overcurrent condition. This
protection feature incorporates a leading edge
blanking circuit following the comparator to improve
noise immunity.
- VCC Under Voltage Lockout protection maintains
the IC in a low current consumption, UVLO mode
during start-up if VCC pin voltage is less than the
VCC turn-on threshold, VCC,ON. In UVLO mode the
current consumption is less than ICC,START which is
typically about 200uA. Should VCC pin voltage
should drop below UVLO threshold VCC, UVLO anytime
after start-up, the IC is pushed back into UVLO mode
(VCOMP pin is discharged) and VCC pin has to
exceed VCC,ON again to re-start operation.
www.irf.com
12 © 2011 International Rectifier

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