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PDF UM10601 Data sheet ( Hoja de datos )
| Número de pieza | UM10601 | |
| Descripción | LPC800 User manual | |
| Fabricantes | NXP Semiconductors | |
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UM10601
LPC800 User manual
Rev. 1.0 — 7 November 2012
Preliminary user manual
Document information
Info
Keywords
Content
ARM Cortex M0+, LPC800, USART, I2C, LPC810M021FN8,
LPC811M001FDH16, LPC812M101FDH16, LPC812M101FD20,
LPC812M101FDH20
Abstract
LPC800 Preliminary user manual
http://www.DataSheet4U.net/
datasheet pdf - http://www.DataSheet4U.net/
1 page  
NXP Semiconductors
UM10601
Chapter 1: LPC800 Introductory information
1.3 Ordering information
Table 1. Ordering information
Type number
Package
LPC810M021FN8
Name
DIP8
LPC811M001FDH16 TSSOP16
LPC812M101FDH16 TSSOP16
LPC812M101FD20 SO20
LPC812M101FDH20 TSSOP20
Description
plastic dual in-line package; 8 leads (300 mil)
plastic thin shrink small outline package; 16 leads; body width 4.4 mm
plastic thin shrink small outline package; 16 leads; body width 4.4 mm
plastic small outline package; 20 leads; body width 7.5 mm
plastic thin shrink small outline package; 20 leads; body width 4.4 mm
Version
SOT097-2
SOT403-1
SOT403-1
SOT163-1
SOT360-1
Table 2. Ordering options
Type number
Flash/kB SRAM/kB USART
LPC810M021FN8
4
1
2
LPC811M001FDH16
8
2
2
LPC812M101FDH16
16
4
3
LPC812M101FD20
16
4
2
LPC812M101FDH20
16
4
3
I2C
1
1
1
1
1
SPI Comparator
11
11
21
11
21
GPIO
6
14
14
18
18
Package
DIP8
TSSOP16
TSSOP16
SO20
TSSOP20
http://www.DataSheet4U.net/
UM10601
Preliminary user manual
All information provided in this document is subject to legal disclaimers.
Rev. 1.0 — 7 November 2012
© NXP B.V. 2012. All rights reserved.
5 of 313
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5 Page 
NXP Semiconductors
UM10601
Chapter 3: LPC800 Nested Vectored Interrupt Controller (NVIC)
Table 3. Connection of interrupt sources to the NVIC
Interrupt Name
number
Description
Flags
3
UART0_IRQ
USART0 interrupt
See Table 161 “USART Interrupt Enable read and set register
(INTENSET, address 0x4006 400C(USART0), 0x4006 800C
(USART1), 0x4006 C00C(USART2)) bit description”
4
UART1_IRQ
USART1 interrupt
Same as UART0_IRQ
5
UART2_IRQ
USART2 interrupt
Same as UART0_IRQ
6-
Reserved
-
7-
Reserved
-
8
I2C0_IRQ
I2C0 interrupt
See Table 175 “Interrupt Enable Clear register (INTENCLR,
address 0x4005 000C) bit description”.
9
SCT_IRQ
State configurable timer
EVFLAG SCT event
interrupt
10
MRT_IRQ
Multi-rate timer interrupt
Global MRT interrupt.
GFLAG0
GFLAG1
GFLAG2
GFLAG3
11
CMP_IRQ
Analog comparator interrupt COMPEDGE - rising, falling, or both edges can set the bit
12
WDT_IRQ
Windowed watchdog timer WARNINT - watchdog warning interrupt
interrupt
13
BOD_IRQ
BOD interrupts
BODINTVAL - BOD interrupt level
14
FLASH_IRQ
Flash interrupt
<tbd>http://www.DataSheet4U.net/
15
WKT_IRQ
Self wake-up timer interrupt ALARMFLAG
23:16
-
Reserved
-
24
PININT0_IRQ Pin interrupt 0 or pattern
PSTAT - pin interrupt status
match engine slice 0
interrupt
25
PININT1_IRQ Pin interrupt 1 or pattern
PSTAT - pin interrupt status
match engine slice 1
interrupt
26
PININT2_IRQ Pin interrupt 2 or pattern
PSTAT - pin interrupt status
match engine slice 2
interrupt
27
PININT3_IRQ Pin interrupt 3 or pattern
PSTAT - pin interrupt status
match engine slice 3
interrupt
28
PININT4_IRQ Pin interrupt 4 or pattern
PSTAT - pin interrupt status
match engine slice 4
interrupt
UM10601
Preliminary user manual
All information provided in this document is subject to legal disclaimers.
Rev. 1.0 — 7 November 2012
© NXP B.V. 2012. All rights reserved.
11 of 313
datasheet pdf - http://www.DataSheet4U.net/
11 Page | ||
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