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PDF AN-214 Data sheet ( Hoja de datos )

Número de pieza AN-214
Descripción Transmission Line Drivers and Receivers
Fabricantes National Semiconductor 
Logotipo National Semiconductor Logotipo



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Transmission Line Drivers
and Receivers for TIA/EIA
Standards RS-422 and
RS-423
Introduction
With the advent of the microprocessor, logic designs have
become both sophisticated and modular in concept. Fre-
quently the modules making up the system are very closely
coupled on a single printed circuit board or cardfile. In a
majority of these cases a standard bus transceiver will be
adequate. However because of the distributed intelligence
ability of the microprocessor, it is becoming common prac-
tice for the peripheral circuits to be physically separated from
the host processor with data communications being handled
over cables (e.g. plant environmental control or security
system). And often these cables are measured in hundreds
or thousands of feet as opposed to inches on a backplane. At
this point the component wavelengths of the digital signals
may become shorter than the electrical length of the cable
and consequently must be treated as transmission lines.
Further, these signals are exposed to electrical noise
sources which may require greater noise immunity than the
single chassis system.
It is the object of this application note to underscore the more
important design requirements for balanced and unbalanced
transmission lines, and to show that National’s DS1691
driver and DS78LS120 receiver meet or exceed all of those
requirements.
The Requirements
The requirements for transmission lines and noise immunity
have been adequately recognized by National Semiconduc-
National Semiconductor
Application Note 214
John Abbott
John Goldie
August 1993
tor’s application note AN-108 and TIA/EIA standards TIA/
EIA-422-B (balanced) and TIA/EIA-423-B (unbalanced). In
this application note the generic terms of RS-422 and
RS-423 will be used to represent the respective TIA/EIA
standards. A summary review of these notes will show that
the controlling factors in a voltage digital interface are:
1. The cable length
2. The data signaling rate
3. The characteristic of the interconnection cable
4. The rise time of the signal
RS-422 and RS-423 contain several useful guidelines rela-
tive to the choice of balanced circuits versus unbalanced
circuits. Figure 1 and Figure 2 are the digital interface for
balanced (1) and unbalanced (2) circuits.
Even though the unbalanced interface circuit is intended for
use at lower modulation rates than the balanced circuit, its
use is not recommended where the following conditions
exist:
1. The interconnecting cable is exposed to noise sources
which may cause a voltage sufficient to indicate a
change of binary state at the load.
2. It is necessary to minimize interference with other sig-
nals, such as data versus clock.
3. The interconnecting cable is too long electrically for
unbalanced operation (Figure 3).
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Legend:
Rt = Transmission line termination and/or receiver input impedance
VGROUND = Ground potential difference
A, B = Driver interface
A', B' = Load interface
C = Driver circuit ground
C' = Load circuit ground
FIGURE 1. Balanced Digital Interface Circuit
00585401
TRI-STATE® is a registered trademark of National Semiconductor Corp.
© 2002 National Semiconductor Corporation AN005854
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AN-214 pdf
Characteristics (Continued)
DRIVER BALANCED (RS-422)
The balanced driver characteristics as specified by RS-422
are as follows:
1. A driver circuit should result in a low impedance (100
or less) balanced voltage source that will produce a
differential voltage applied to the interconnecting cable
in the range of 2V to 10V.
2. With a test load of 2 resistors, 50each, connected in
series between the driver output terminals, the magni-
tude of the differential voltage (VT) measured between
the 2 output terminals shall not be less than either 2.0V
or 50% of the magnitude of VO, whichever is greater. For
the opposite binary state the polarity of VT shall be
reversed (VT ). The magnitude of the difference in the
magnitude of VT and VT shall be less than 0.4V. The
magnitude of the driver offset voltage (VOS) measured
between the center point of the test load and driver
circuit ground shall not be greater than 3.0V. The mag-
nitude of the difference in the magnitude of VOS for one
binary state and VOS for the opposing binary state shall
be less than 0.4V.
3. During transitions of the driver output between alternat-
ing binary states, the differential signal measured across
a 100test load connected between the driver output
terminals shall be such that the voltage monotonically
changes between 0.1 and 0.9 of VSS within 10% of the
unit interval or 20 ns, whichever is greater. Thereafter
the signal voltage shall not vary more than 10% of VSS
from the steady state value, until the next binary transi-
tion occurs, and at no time shall the instantaneous mag-
nitude of VT or VT exceed 6V, nor less than 2V.
INTERCONNECTING CABLE
The characteristics of the interconnecting cable should result
in a transmission line with a characteristic impedance in the
general range of 100to frequencies greater than 100 kHz,
and a DC series loop resistance not exceeding 240. The
cable may be composed of twisted or untwisted pair (flat
cable) and is not further specified within the standards.
1. Conductor size of the 2 wires 24 AWG or larger, and wire
resistance not to exceed 30per 1000 feet per conduc-
tor.
2. Mutual pair capacitance between 1 wire in the pair to the
other should be less than 20 pF/ft.
00585408
00585409
tb = Time duration of the unit interval at the applicable modulation rate.
tr 0.1 tb when tb 200 ns
tr 20 ns when tb < 200 ns
VSS = Difference in steady state voltages
VSS = |Vt − Vt|
FIGURE 7. Balanced Driver Output Signal Waveform
RECEIVER
The receiver characteristics are identical for both balanced
(RS-422) and unbalanced (RS-423) circuits. The electrical
characteristics of a single receiver without termination or
optional fail-safe provisions are specified as follows:
1. Over an entire common-mode voltage range of −7V to
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+7V, the receiver shall not require a differential input
voltage of more than 200 mV to correctly assume the
intended binary state. The common-mode voltage (VCM)
is defined as the algebraic mean of the 2 voltages
appearing at the receiver input terminals with respect to
the receiver circuit ground. Reversing the polarity of VT
shall cause the receiver to assume the opposite binary
state. This allows for operations where there are ground
differences caused by IR drop and noise of up to ±7V.
2. To maintain correct operation for differential input signal
voltages ranging between 200 mV and 6V in magnitude.
3. The maximum voltage present between either receiver
input terminal and receiver circuit ground shall not ex-
ceed 10V (3V signal plus 7V common-mode) in magni-
tude nor cause the receiver to operationally fail. Addi-
tionally, the receiver shall tolerate a maximum
differential signal of 12V applied across its input termi-
nals without being damaged.
4. The total load including up to 10 receivers shall not have
a resistance less than 90for balanced, and 450for
unbalanced at its input points and shall not require a
differential input voltage of greater than 200 mV for all
receivers to assume the correct binary state.
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AN-214 arduino
Fail-Safe Operation (Continued)
00585422
00585423
00585424
FIGURE 18. Fail-Safe Using the DS88LS120 Threshold Offset for Unbalanced Lines
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00585425
00585426
00585427
00585428
FIGURE 19. Fail-Safe Using the DS88LS120 Threshold Offset for Balanced Lines
Conclusion
This application note provides a brief overview of TIA/
EIA-422-B and TIA/EIA-423-B. At the time of publication of
this application note the Rev. B standards were draft stan-
dard proposals only. For complete/current information on the
respective standards the reader is referenced to the respec-
tive standards, as minor differences may exist between this
document and the final versions.
11
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